UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45212

13.3 - ISIM: Assertion fatal error

Description

ISIM crashes when the assert command and  the 'delayed attribute are used inside the same process.


This error is received in the testbench.:

FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 10551

Solution

 

Example Code:

 CHECK_TIMING: process
    begin
      wait until falling_edge(test_signal);
      assert test_signal'delayed'stable(100 ns)  -- Check pulse width
      report "Pulse width of test_signal was < 100 ns, pulse width was: " & time'image(test_signal'delayed'last_event)
      severity WARNING;
    end process;

 

Removing the line with the 'delayed attribute from the above code will not result in any errors.

The code will also work if the line containing the assert command is commented out.

This can be used as a workaround but it always prints the sentence.

 

This seems to be a compilation error from the VhdlExpr.cpp library.

AR# 45212
Date Created 11/30/2011
Last Updated 10/23/2014
Status Active
Type General Article