Additive Latency is an efficiency feature in SDRAM memories. It is discussed in section 220.127.116.11 of JEDEC Specification JESD79-3 DDR3 SDRAM Standard and 2.5 of JEDEC Specification JESD79-2 DDR2 SDRAM Standard (in the "Bank activate command" section). Additive latency allows a read or write command to be issued immediately following the active command.
The MIG 7 Series DDR3/DDR2 design is generated with AL=0. Are non-zero AL values supported?
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The MIG 7 Series DDR3/DDR2 controller does not support non-zero AL values. The controller is designed to use an intelligent look-ahead and re-order logic that results in higher efficiency than the usage of non-zero AL.
The 7 Series MIG DDR3 PHY is supported standalone to use with a custom controller, and the hard blocks used within the PHY do have support built in for non-zero AL. The PHY calibration MUST operate with additive latency equal to 0 (AL = 0). When using the 7 Series MIG DDR3 PHY standalone, if it is desired to use a non-zero additive latency (CL-1 or CL-2) AFTER the completion of calibration, then the controller must issue the appropriate MRS command. Furthermore, the data offset used in the PHY Control Word must be recalculated with the addition of the AL value.
When MIG1.9 or later version is used with non-zero AL and PHY alone requirement, please use the attachment to replace the initialization module. Write calibration will be stuck at sanity write calibration when TEST_AL is set to non zero value. The attachment at the end of this answer record will make the calibration succeed with AL=0, then program non-zero AL to memory chip.