UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45281

13.3 EDK, AXI_V6_DDRx - Lower memory throughput in EDK 13.3 only

Description

In EDK 13.3 software, reduced memory throughput is seen relative to 13.2 when using the AXI_V6_DDRx controller. How do I resolve this issue?

Solution

The reduced throughput may be caused by an error in theC_RD_WR_ARB_ALGORITHM parameter.This parameter determines the arbitration between the read and write channels of the AXI interface.

To revert to the arbitration scheme used in 13.2 and earlier, add the following line to the MHS file in each controllers instance:

PARAMETER C_RD_WR_ARB_ALGORITHM = RD_PRI_REG

This issue is fixed in the latest version starting with EDK 13.4 software.
AR# 45281
Date Created 12/05/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
Tools
  • EDK - 13.3