Port "Buffer" is not supported with ISIM. The following errors occur:
"ERROR:HDLCompiler:439 - "C:/XXX/XXX/XX.vhd" Line 46: Formal port<xxx> of mode buffer cannot be associated with actual port<xxx> of mode out"
"ERROR:Simulator:777 - Static elaboration of top level VHDL design unitXX in library work failed"
Theseerrors can occurif any port is declared as abuffer.You might need to declare the VHDL buffered port as output and use an intermediate signal to perform read and write operation on it, and later assign the intermediate signal to the output port. See the following example:
entity alu is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
CLK : in STD_LOGIC;
C : buffer STD_LOGIC_VECTOR(3 downto 0) );
end alu;
architecture BEHAVIORAL of alu is
begin
process begin
if (CLK'event and CLK='1') then
C <= UNSIGNED(A) + UNSIGNED(B) UNSIGNED(C);
end if;
end process;
end BEHAVIORAL;
Modified code:
entity alu is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
CLK : in STD_LOGIC;
C : out STD_LOGIC_VECTOR(3 downto 0)
);
end alu;
architecture BEHAVIORAL of alu is
-- dummy signal
signal C_INT : STD_LOGIC_VECTOR(3 downto 0);
begin
C <= C_INT;
process begin
if (CLK'event and CLK='1') then
C_INT <= A and B and C_INT;
end if;
end process;
end BEHAVIORAL;
For more information on ports, see theSynthesis and Simulation Guide, as well as the ISIM User Guide.