1. GTX Transceiver Attribute Updates for General Engineering Sample (ES) Silicon
This table shows the GTX attribute updates required for reliable operation of the General ES silicon.
The Initial ES bitstream cannot be used with General ES silicon and vice versa. ISE Design Suite 13.4 generates the following attribute updates natively when using v1.6 of the 7 series FPGA Transceiver Wizard. Version 1.5 of the Wizard only supports the Initial ES Silicon settings and version 1.6 supports only the General ES Silicon settings in ISE 13.4.
The General ES bitstream generated with v2.1 or earlier of the wizard cannot be used with Production silicon and vice versa. When using ISE Design Suite 14.2, 7 series FPGA Transceiver Wizard version 2.2 must be used for the General ES silicon and this bitstream is compatible with GTX production silicon. However, for the latest RXCDR_CFG settings in the table below, v2.3 of the wizard in ISE 14.3/Vivado 2012.3 must be used and this version supports both General ES and production GTX. If using ISE 14.4/Vivado 2012.4, v2.4 must be used and this version supports both General ES and Production GTX silicon. For information on different silicon revisions supported by the wizard versions, please refer to (Xilinx Answer 46048).
Attribute |
Value |
|||
BIAS_CFG | 64'h0000040000001000 |
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CPLL_CFG | 24'hBC07DC | |||
QPLL_CFG |
QPLL Lower band: 27'h06801C1 QPLL Upper band: 27'h0680181 |
|||
QPLL_LOCK_CFG |
16'h21E8 |
|||
QPLL_CP | 10'h01F | |||
QPLL_LPF |
4'hF |
|||
RXCDR_FR_RESET_ON_EIDLE |
1'b0 |
|||
RXCDR_PH_RESET_ON_EIDLE | 1'b0 |
|||
RXCDR_HOLD_DURING_EIDLE |
1'b0 |
|||
RX_DEBUG_CFG | 12'h000 | |||
RXCDR_CFG | Full-rate(1) | Half-rate(2) | Quarter-rate(3) | One-eighth rate(4) |
Scrambled and 8B/10B with Pre-scrambling patterns | CDR setting < +/- 200 ppm LPM mode: 72'h0B_0000_23FF_1040_0020 (> 6.6 Gb/s) 72'h03_0000_23FF_1020_0020 (<= 6.6 Gb/s) DFE mode: 72'h0B_0000_23FF_1040_0020 (> 6.6 Gb/s) 72'h03_0000_23FF_2040_0020 (<= 6.6 Gb/s)
CDR setting < +/- 700 ppm LPM mode: 72'h0B_8000_23FF_1040_0020 (> 6.6 Gb/s) 72'h03_8000_23FF_1020_0020 (<= 6.6 Gb/s) DFE mode: 72'h0B_8000_23FF_1040_0020 (> 6.6 Gb/s) 72'h03_8000_23FF_2040_0020 (<= 6.6 Gb/s) CDR setting < +/- 1250 ppm
LPM mode:
72'h0B_8000_23FF_1020_0020 (> 6.6 Gb/s) 72'h03_8000_23FF_1020_0020 (<= 6.6 Gb/s)
DFE mode:
72'h0B_8000_23FF_1020_0020 (> 6.6 Gb/s) 72'h03_8000_23FF_1020_0020 (<= 6.6 Gb/s)
|
CDR setting < +/- 200 ppm LPM/DFE mode: 72'h03_0000_23FF_4020_0020
CDR setting < +/- 700 ppm LPM/DFE mode: 72'h03_8000_23FF_4020_0020
CDR setting < +/- 1250 ppm LPM/DFE mode: 72'h03_8000_23FF_4020_0020
|
CDR setting < +/- 200 ppm LPM/DFE mode: 72'h03_0000_23FF_4010_0020
CDR setting < +/- 700 ppm LPM/DFE mode: 72'h03_8000_23FF_4010_0020
CDR setting < +/- 1250 ppm LPM/DFE mode: 72'h03_8000_23FF_4010_0020 |
CDR setting < +/- 200 ppm LPM/DFE mode: 72'h03_0000_23FF_4008_0020
CDR setting < +/- 700 ppm LPM/DFE mode: 72'h03_8000_23FF_4008_0020
CDR setting < +/- 1250 ppm LPM/DFE mode: 72'h03_8000_23FF_4008_0020 |
8B/10B without Pre-scramble pattern | CDR setting < +/- 200 ppm LPM mode: 72'h03_0000_23FF_1040_0020
CDR setting < +/- 700 ppm LPM mode: 72'h03_8000_23FF_1040_0020
CDR setting < +/- 1250 ppm LPM mode: 72'h03_8000_23FF_1040_0020 |
CDR setting < +/- 200 ppm LPM mode: 72'h03_0000_23FF_1020_0020
CDR setting < +/- 700 ppm LPM mode: 72'h03_8000_23FF_1020_0020
CDR setting < +/- 1250 ppm LPM mode: 72'h03_8000_23FF_1020_0020 |
CDR setting < +/- 200 ppm LPM mode: 72'h03_0000_23FF_1010_0020
CDR setting < +/- 700 ppm LPM mode: 72'h03_8000_23FF_1010_0020 CDR setting < +/- 1250 ppm LPM mode: 72'h03_8000_23FF_1010_0020 |
CDR setting < +/- 200 ppm LPM mode: 72'h03_0000_23FF_1008_0020 CDR setting < +/- 700 ppm LPM mode: 72'h03_8000_23FF_1008_0020 CDR setting < +/- 1250 ppm LPM mode: 72'h03_8000_23FF_1008_0020 |
SATA REFCLK PPM with SSC setting(5) | 72'h03_8000_8BFF_1020_0010 (Gen 3 at 6 Gb/s) | 72'h03_8800_8BFF_4020_0008 (Gen 2 at 3 Gb/s) | 72'h03_8000_8BFF_4010_0008 (Gen 1 at 1.5 Gb/s) | |
RXCDR_LOCK_CFG |
6'b010101(6) |
|||
RX_BIAS_CFG | 12'b000000000100 | |||
RX_OS_CFG |
13'b0000010000000 | |||
RX_DFE_LPM_HOLD_DURING_EIDLE | 1'b0 | |||
PMA_RSV | 32'h 0001_8480(7) 32'h 001E_7080(8) | |||
PMA_RSV2[5] | 1'b1 (9) 1'b0 (10) | |||
ES_EYE_SCAN_EN | TRUE | |||
RX_CM_SEL | 2'b11 | |||
PMA_RSV2[4], RX_CM_TRIM | 1'b1, 3'b010 (11) | |||
PCS_RSVD_ATTR[8] | 1'b1(12) 1'b0(13) | |||
RX_DFE_XYD_CFG | 13'h0000 | |||
DFE mode | Internal Serial Loopback | Channel | ||
RX_DFE_GAIN_CFG | 23'h0207EA | 23'h020FEA | ||
RX_DFE_VP_CFG | 17'b00011111100000011 | 17'b00011111100000011 | ||
RX_DFE_UT_CFG | 17'b10001000000000000 | 17'b10001111000000000 | ||
RX_DFE_KL_CFG | 13'b0000011111110 | 13'b0000011111110 | ||
RX_DFE_KL_CFG2 | 32'h3788140A | As per user guide (UG476) use models(14) | ||
RX_DFE_H2_CFG | 12'b000110000000 | 12'b000000000000 | ||
RX_DFE_H3_CFG | 12'b000110000000 |
12'b000001000000 | ||
RX_DFE_H4_CFG | 11'b00011100000 | 11'b00011110000 | ||
RX_DFE_H5_CFG | 11'b00011100000 | 11'b00011100000 | ||
RX_DFE_LPM_CFG | 16'h0954 | 16'h0954 | ||
LPM mode | Short channel (<=2.5 dB loss) | Long channel (>2.5 dB loss) | ||
RXLPM_HF_CFG | 14'b00000000000000 | 14'b00000011110000 | ||
RXLPM_LF_CFG | 14'b00000000000000 | 14'b00000011110000 | ||
RX_DFE_LPM_CFG | 16'h0904(15) 16'h0104(16) |
16'h0904(15) 16'h0104(16) |
Notes:
2. General ES Silicon GTX Errata Items
This section refers to the Kintex-7 FPGA CES errata for General ES silicon.
The GTX transceiver CPLL can become inoperative if conditions (a) and (b) persist for greater than 8,000 hours:
When the QPLL is being used, enabling each CPLL will consume up to 30 mA on the MGTAVTT supply and 20 mA on MGTAVCC.
This requires that the CPLL always be powered on even when only the QPLL is used by setting the CPLL powerdown port CPLLPD always to 1'b0.
3. Use Modes
Eye Scan Use mode
ES_EYE_SCAN_EN | PMA_RSV2[5] | Description |
TRUE | 1'b0 | Eye Scan disabled |
TRUE | 1'b1 | Eye Scan enabled |
OOB Use Mode
PCS_RSVD_ATTR[8] | Description |
1'b0 | OOB powered down |
1'b1 | OOB powered on |
NOTE: OOB circuitry must be powered on for applications such as PCI Express, SATA/SAS.
4. GTX Software Known Issues/Use Mode Changes
For the latest GTX software use mode changes and known issues, please refer to (Xilinx Answer 43339).
5. Initial ES to General ES Migration for GTX
For customers looking at migrating designs using GTX from Initial ES to General ES silicon, there are several things to consider as discussed in (Xilinx Answer 45410).
Revision History
05/05/2014 - Updated the RXCDR_CFG setting for SATA Gen 2/Gen 3 and PMA_RSV for 6.6 Gbps
11/22/2013 - Updated the table to refer to the user guide UG476 for RX_DFE_KL_CFG2 setting since it is channel dependent.
12/12/2012 - Added the RXCDR_CFG setting for SATA SSC and added a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.
10/18/2012 - Added/updated RXCDR_CFG settings for scrambled/non-scrambled 8B/10B and non-8B/10B patterns.
07/19/2012 - Added the RX_DFE_XYD_CFG value to the attributes table.
06/28/2012 - Updated GTX software use mode changes (Xilinx Answer 43339) with the latest GTXE2_COMMON use model change information.
03/22/2012 - Updated RXCDR_CFG settings for half-rate mode.
02/22/2012 - Added RXCDR_CFG settings for quarter-rate and one-eighth rate. Added a link to GTX software known issues/use mode changes.
01/12/2012 - Initial release
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |
47690 | LogiCORE IP XAUI v10.3 - VHDL wrappers need update to RXCDR_CFG attribute for 7 series GTX Transceiver | N/A | N/A |
42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |
AR# 45360 | |
---|---|
Date | 05/23/2014 |
Status | Active |
Type | Design Advisory |
Devices |