I generated a Triple SDI or CIC Compiler corethrough the PlanAhead IP Catalog and instantiated it in my design. Now, when I synthesize the design using XST, I see an error similar to the following.
Parsing architecture <virtex6l> of entity <my_v_triple_sdi>. Parsing VHDL file "/Project_dir/v_triple_sdi_v1.0/run/pa_project/pa_project.runs/synth_1/my_v_triple_sdi_sim.vhd" into library work ERROR:HDLCompiler:104 - "/Project_dir/v_triple_sdi_v1.0 /run/pa_project/pa_project.runs/synth_1/my_v_triple_sdi_sim.vhd" Line 42: Cannot find <dru> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. Parsing entity <my_v_triple_sdi>. ERROR:HDLCompiler:854 - "/Project_dir/v_triple_sdi_v1.0 /run/pa_project/pa_project.runs/synth_1/my_v_triple_sdi_sim.vhd" Line 44: Unit <my_v_triple_sdi> ignored due to previous errors.
In ISE Design Suite 13.2, the PlanAhead IP generation for these cores is delivering some of the IP core simulation files as synthesis files as well.
To work around this issue in ISE Design Suite 13.2, the IP core would have to be removed from the project and all of the generated IP core files added to the project appropriately.
This issue has been fixed in ISE Design Suite 13.3.