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  3. AR# 4544: A1.5 CPLD - CPLD update is available with faster speed grades and other changes.
  4. AR# 45447: MIG 7 Series RLDRAM II and QDRII+ - Skew on the K/K# clocks can cause calibration failures

AR# 45447

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MIG 7 Series RLDRAM II and QDRII+ - Skew on the K/K# clocks can cause calibration failures

Description

Version Found: v1.3
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

In some cases, MIG 7 Series RLDRAM II and QDRII+ designs can fail calibration as a result of skew on the K/K# output clocks sent to the memory.

This can cause addresses and data to be clocked into the memory incorrectly and cause calibration to fail.

Solution

The reason for this is a result of how the PO_OCLK_DELAY parameter is defined in the qdr_rld_mc_phy module, as there are no additional assignments for frequencies less than 666.67 MHz. 

For example, the qdr_rld_mc_phy.v file (for the Verilog code generated) uses:

localparam integer PO_OCLK_DELAY = (SIMULATION == "TRUE") ? MC_OCLK_DELAY :

(CLK_PERIOD <= 938) ? 23 :
(CLK_PERIOD <= 1072) ? 24 :
(CLK_PERIOD <= 1250) ? 25 :
(CLK_PERIOD <= 1500) ? 26 : 27;



If you are targeting an RLDRAM II design then replace lines 325-360 in qdr_rld_mc_phy.v with the following to work around the issue:
 

//*******************************************************************************************************************
// OCLK_DELAYED 90 degree phase shift calculations
//*******************************************************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz and 1.25 for Mem_RefClk > 300 MHz

localparam PO_OCLKDELAY_INV = ((SIMULATION == "FALSE" && CLK_PERIOD > 2500) || CLK_PERIOD>= 3333) ? "FALSE" : "TRUE";

//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, DIV4: MemRefClk < 200 MHz

localparam PHY_FREQ_REF_MODE = CLK_PERIOD > 5000 ? "DIV4" : CLK_PERIOD > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_FREQ_REF_MODE == "DIV4" ? 4 : PHY_FREQ_REF_MODE == "DIV2" ? 2 : 1);

//FreqRefClk (MHz) is 1,2,4 times faster than MemRefClk

localparam real FREQ_REF_MHZ = 1.0/((CLK_PERIOD/FREQ_REF_DIV/1000.0) / 1000) ;
localparam real MEM_REF_MHZ = 1.0/((CLK_PERIOD/1000.0) / 1000) ;

// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output

localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/CLK_PERIOD; // Fraction of MemRefClk

// Whether OCLK_DELAY output comes inverted or not

localparam real HALF_CYCLE_DELAY = 0.5 * (PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); //Fraction of MemRefClk

// Phaser-Out Stage3 Tap delay for 90 deg shift. Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/63/FREQ_REF_DIV;
// Equation: INT_DELAY + HALF_CYCLE_DELAY + TAP_DELAY = 0.25 or 1.25 MemRefClk cycles

localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV;

//localparam integer PO_OCLK_DELAY = MC_OCLK_DELAY; // MC_OCLK_DELAY + 0.5;

localparam integer PO_OCLK_DELAY
= (SIMULATION == "TRUE") ? MC_OCLK_DELAY :
(CLK_PERIOD > 2500) ? 8 :
(CLK_PERIOD <= 938) ? 23 :
(CLK_PERIOD <= 1072) ? 24 :
(CLK_PERIOD <= 1250) ? 25 :
(CLK_PERIOD <= 1500) ? 26 : 27;



If you are targeting a QDRII+ design then replace lines 325-360 in qdr_rld_mc_phy.v with the following to work around the issue:
 

//*******************************************************************************************************************
// OCLK_DELAYED 90 degree phase shift calculations
//*******************************************************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = ((SIMULATION == "FALSE" && CLK_PERIOD > 2500) || CLK_PERIOD>= 3333) ? "FALSE" : "TRUE";

//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, DIV4: MemRefClk < 200 MHz
localparam PHY_FREQ_REF_MODE = CLK_PERIOD > 5000 ? "DIV4" : CLK_PERIOD > 2500 ? "DIV2": "NONE";

localparam FREQ_REF_DIV = (PHY_FREQ_REF_MODE == "DIV4" ? 4 : PHY_FREQ_REF_MODE == "DIV2" ? 2 : 1);

//FreqRefClk (MHz) is 1,2,4 times faster than MemRefClk
localparam real FREQ_REF_MHZ = 1.0/((CLK_PERIOD/FREQ_REF_DIV/1000.0) / 1000) ;
localparam real MEM_REF_MHZ = 1.0/((CLK_PERIOD/1000.0) / 1000) ;

// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/CLK_PERIOD; // Fraction of MemRefClk

// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5 * (PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); //Fraction of MemRefClk

// Phaser-Out Stage3 Tap delay for 90 deg shift. Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/63/FREQ_REF_DIV;

// Equation: INT_DELAY + HALF_CYCLE_DELAY + TAP_DELAY = 0.25 or 1.25 MemRefClk cycles
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV;
//localparam integer PO_OCLK_DELAY = MC_OCLK_DELAY; // MC_OCLK_DELAY + 0.5;

localparam integer PO_OCLK_DELAY
= (SIMULATION == "TRUE") ? MC_OCLK_DELAY :
(CLK_PERIOD > 2500) ? 8 : 1;

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 45447
Date 08/21/2014
Status Active
Type Known Issues
Devices
Tools
IP
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