We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45470

13.2 PlanAhead - [Constraints 5] Cannot loc terminal 'my_sig_P' at site U36, Invalid site for GT's clock signal


In the PlanAhead 13.2 software, I receive several critical warnings similar to the following:

"[Constraints 5] Cannot loc terminal 'my_sig_P' at site U36, Invalid site for GT's clock signal

The warnings refer to GT clock signals, but the design signals associated with the constraints are differential signals not associated with a GT.

My design does place and route, however, the constraints flagged in the Critical Warnings are not followed.

NOTE: The same design completes Place and Route in Project Navigator without errors or warnings related to these pins.


The PlanAhead 13.2 DRC check incorrectly flags the pins as associated with a GT.Because of the critical warnings, the constraints are removed from the intermediate UCF used for implementation.

This issue has been fixed in the PlanAhead tool 13.3.

To work around the issue in PlanAhead 13.2, apply the LOC constraints in another UCF directly to NGDBuild via the "-uc" switch.This can be performed by selecting the Synthesis Settings option and typing "-uc" followed by the directory and file name (e.g., "-uc C:\my_project\diff signals.ucf") in the "More Options" field.

AR# 45470
Date 05/16/2012
Status Active
Type Known Issues
  • PlanAhead - 13.2
Page Bookmarked