We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45485

CORE Generator - "ERROR:sim - Unknown language preference 'None'"


IP Core generation fails with the following message:

"ERROR:sim - Unknown language preference 'None'."


This error can occur when neither VHDL nor Verilog outputs are chosen in the project options. This state should only be possible if a user has edited the ".xco" file outside of the CORE Generator tool.

The use case of selecting neither VHDL nor Verilog is very rare; it is only available by editing the ".xco" files.

Before generating the core, verify that either the vhdlsim or verilogsim property is set to "true".
AR# 45485
Date 05/26/2014
Status Archive
Type Known Issues
  • ISE Design Suite - 13.3