CORE Generator - "ERROR:sim - Unknown language preference 'None'"
IP Core generation fails with the following message:
"ERROR:sim - Unknown language preference 'None'."
This error can occur when neither VHDL nor Verilog outputs are chosen in the project options. This state should only be possible if a user has edited the ".xco" file outside of the CORE Generator tool.
The use case of selecting neither VHDL nor Verilog is very rare; it is only available by editing the ".xco" files.
Before generating the core, verify that either the vhdlsim or verilogsim property is set to "true".