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  3. AR# 4549: Is 4085xl BG560 footprint(pin) compatible with 40125xv ? (4000xl, 4000xv)
  4. AR# 45497: LogiCORE IP XAUI v10.1/v10.2 - sync_status is deasserted during data transfer on Kintex-7 and Virtex-7 Initial or General ES devices

AR# 45497

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LogiCORE IP XAUI v10.1/v10.2 - sync_status is deasserted during data transfer on Kintex-7 and Virtex-7 Initial or General ES devices

Description

During data transfer on Kintex-7 or Virtex-7 Initial ES or General ES devices,sync_status is de-asserted. I do not see rxnotintable or rxdisperr being asserted.

Solution

To work around this issue, make thefollowing changesin the*_block.vhd (v) file:

Verilog:

From:
mgt_rxlock_r1 <= mgt_rxlock and (not mgt_rxelecidle_i) ;
To:
mgt_rxlock_r1 <= {4{mgt_plllocked}};

VHDL:

From:
mgt_rxlock_r1 <= mgt_rxlock and (not mgt_rxelecidle_i) ;
To:
mgt_rxlock_r1 <= (mgt_plllocked & mgt_plllocked & mgt_plllocked & mgt_plllocked);

Revision History
03/06/2012 - Fixed typo
02/27/2012 - Updated to include General ES devices
01/26/2012 - Updated to include Virtex-7 Initial ES deviceand XAUI v10.2
12/17/2011 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43244 Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon N/A N/A
AR# 45497
Date 05/19/2012
Status Active
Type Known Issues
IP
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