AR# 45518


Vivado HLS - Checklist for DSP48s mappings


Checklist for DSP48s mappings.


Vivado HLS relies on synthesis tools such as Synplify, XST, or Vivado Synthesis to infer operation patterns such MAC or pre-adder in DSP48 primitives. The following checklist provides possible reasons for the lack of DSP48 primitives.
  1. Constant multiplications: Constant multiplications can sometimes be implemented using shift-add-sub efficiently, and Vivado HLS may eliminated the need for a multiplication and thus a MAC.
  2. Multiplier fanout: If the result of a multiplication is used by multiple other operations, it often cannot be combined with a post-adder. Therefore, it is better if the post-adder has the fanout.
  3. Bit-widths: The bit-widths of the two operands need to fit into the DSP48. For example, 25x18 for a DSP48E/E1 and 18x18 for a DSP48A/A1 and the result should be less than 48 bits. Refer to the user guide for more information on DSP primitive for the device.(Xilinx Documentation - User Guide)
  4. Operand signs: DSP48 inputs are signed; therefore use signed data types for multiplications whenever possible.
  5. Resource assignment: If the operation is associated with CORE Generator IP core through the resource directive, the operation will be implemented as is described by the IP core.
  6. Synthesis tool preference: It is possible for the synthesis tool to avoid inferring DSP48 primitive.
After verifying the items listed in the checklist and Vivado HLS' output still doesn't result in expected DSP48 implementation, contact Xilinx technical support for additional assistance.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 45518
Date 08/14/2012
Status Active
Type Solution Center
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