GTX Transceiver attribute updates are required for ES Silicon to work in hardware.
Please refer to the master (Xilinx Answer 43244) for the latest updates.
Below are the hardware configurations validated in Kintex-7 FPGA KC724 board-to-board setup:
Aurora 8B10B v7.1 core:
Validated core configuration:
Aurora lanes : 4
Line rate : 4.0 Gbps
GT reference clock : 100.0 MHz
Lane Width : 2
Dataflow : Duplex
The GTX Transceiver settings file (aurora_8b10b_v7_1_gt.v) is attached for reference.
Aurora 64B66B v6.1 core:
Validated core configuration:
Aurora lanes : 1
Line rate : 3.125 Gbps
GT reference clock : 156.25 MHz
Lane Width : 8
Dataflow : Duplex
The GTX Transceiver settings file (aurora_64b66b_v6_1_gt.v) is attached for reference.
Note:
Name | File Size | File Type |
---|---|---|
aurora_8b10b_v7_1_gt.v | 38 KB | V |
aurora_64b66b_v6_1_gt.v | 37 KB | V |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
43390 | Kintex-7 FPGA KC724 Characterization Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
52383 | Virtex-7 FPGA VC7203 Characterization Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
54015 | Virtex-7 FPGA VC7222 GTH and GTZ Transceiver Characterization Board - Known Issues and Release Notes Master Answer Record | N/A | N/A |
AR# 45602 | |
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Date | 01/28/2015 |
Status | Active |
Type | General Article |
Devices | |
IP | |
Boards & Kits |