AR# 45623: 13.4 EDK, axi_plbv46_bridge - Netlist simulations hang during write data phase
AR# 45623
13.4 EDK, axi_plbv46_bridge - Netlist simulations hang during write data phase
Description
When doing a netlist-based simulation using the axi_plbv46_bridge, the core freezes during the write data phase.
Is this a known issue? How can we fix this?
Solution
This is a known issue. A workaround is to edit the line #439 in wr_data_sm_full_word.vhd to change the fsm encoding style from "one-hot" to "sequential".
attribute fsm_encoding of wr_data_pr_state: signal is "one-hot"; # default code. attribute fsm_encoding of wr_data_pr_state: signal is "sequential"; # modified code.
This issue is currently planned to be fixed starting in EDK 14.1 software.