The overallreadlatency of the MIG 7 Series DDR3/DDR2 coreis dependent on how the memory controlleris configured,butmost critically on the target traffic/access pattern.Read latency is measured from the point where the read command is accepted by the UI or native interface. In general, read latency varies based on several parameters:
- The number of commands already in the pipeline before the read command is issued
- Whether an ACTIVATE command needs to be issued to open the new bank/row
- Whether a PRECHARGE command needs to be issued to close a previously opened Bank
- Specific timing parameters for the memory, such as TRAS and TRCD in conjunction with the bus clock frequency
- Commands can be interrupted, and banks/rows can forcibly be closed when the periodic AUTO REFRESH command is issued
- CAS latency
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.