We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45646

13.1, 13.2, 13.3, 13.4 Kintex-7, Virtex-7 - GTX IBERT does not work when using 32-bit DATA_WIDTH


When I use the Kintex-7 or Virtex-7 FPGA GTX IBERT core with a 32-bit DATA_WIDTH, the IBERT design does not work (GTs do not link at all).


This issue only affects users who use IBERT under the following conditions:

  • Using 13.1, 13.2, 13.3, or 13.4versions of ISE designtools.
  • Targeting a Kintex-7 or Virtex-7 device.
  • Using a 32-bit DATA_WIDTH when generating the IBERT core

In software versions 13.4 and earlier, the timing constraints are not written correctly for the 32-bit version of the core, which causes it to miss timing during implementation.This causes linking problems with the 32-bit data width IBERT designs.

To work around this issue, do not select 32-bit data widths when generating the core; use a 40-bit data width instead. This issue will be addressed in ISE Design Suite 14.1.

AR# 45646
Date 05/19/2012
Status Active
Type Known Issues
Tools More Less
Page Bookmarked