I am trying to implement the example design from XAPP551 but am receiving the following errors:
ERROR:NgdBuild:604 - logical block 'u0' with type 'viterbi_v7_0' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'viterbi_v7_0' is not supported in target 'virtex6'.
WARNING: the Core Generator generated file 'viterbi_v7_0.ngc' was not found in 'C:/p4workspace/NRRT/Xilinx Projects/Viterbi_Decoder_w_Tail_Biting/tail_biting/ipcore_dir/'.
WARNING: the Core Generator generated file 'viterbi_v7_0.ngc' was not found in 'C:/p4workspace/NRRT/Xilinx Projects/Viterbi_Decoder_w_Tail_Biting/tail_biting/ipcore_dir'.
WARNING:HDLCompiler:89 - "C:\p4workspace\NRRT\Xilinx Projects\Viterbi_Decoder_w_Tail_Biting\tail_biting\vitdec_top.vhd" Line 49: <viterbi_v7_0> remains a black-box since it has no binding entity.
This is a common error related to IP cores.
It indicates that ISE cannot find the .ngc that gets created when the core is generated.
To resolve this, highlight the core in ISE and select 'Regenerate Core.'
This will put the .ngc in the ipcore_dir where ISE looks for IP.
You will now be able to re-generate without issue.