AR# 45671

Description

This Answer Record contains the Release Notes for the Aurora 64B/66B v6.2 core, released in ISE Design Suite 13.4, and includes the following:

• New Features
• Supported Devices
• Resolved Issues
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

New Features

ISE 13.4 software support

• Kintex-7 and Virtex-7 FPGAimplementation support added
• SLR based REFCLK restriction on applicable Virtex-7 devices
• DRP Interface to user

Supported Devices

• Virtex-6 XC LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Virtex-7
• Virtex-7 XT (7vx485t)
• Virtex-7 -2L
• Kintex-7
• Kintex-7 -2L

Resolved Issues

1. Virtex-6QL devices are not supported
Description: Core is not enabled when Virtex-6QL devices are selected
2. Unroutable Placement on BUFDS/GT clock component pair
Description: 7 series FPGA designs error out due to unroutable BUFDS/GT pair
3. Data Frame missing on RX side
Description: Missing one data frame on receive side
4. BitGen errors for 7 series FPGA designs
Description: BitGen errors for 7 series FPGA designs

Known Issues

The following are known issues for v6.2 of this core at the time of release:

1. Virtex-6 HXT/GTH selection of quads should be consecutive
Description: In Virtex-6 HXT/GTH, for line rates >9.8G, the quad selection should be consecutive
There cannot be an unused quad between two used quads
2. Virtex-6 HXT/GTH ES/PS attribiute settings
Description: Refer to Aurora 64B66B v5.1 for ES settings of GTH transceivers
Refer to Aurora 64B66B v6.1 for PS settings of GTH transceivers