This Answer Record contains the Release Notes for the Aurora 8B/10B v5.3 Core, released in ISE Design Suite 13.4, and includes the following:
General Information New Features Bug Fixes Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the
IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.
ISE 13.4 software support Virtex-6 -1L XQ family support Cadence Incisive Enterprise Simulator (IES) support Synopsys Synplify Pro support ISIM support
Virtex-6 XC CXT/LXT/SXT/HXT Virtex-6 XQ LXT/SXT Virtex-6 -1L XC LXT/SXT Virtex-6 -1L XQ LXT/SXT Spartan-6 XC LXT Spartan-6 XA LXT Spartan-6 XQ LXT Virtex-5 XC LXT/SXT/FXT/TXT Virtex-5 XQ LXT/SXT/FXT
line rate at 1,5625G with Refclk at 156.25Mhz doesn't generate core for Spartan-6 Symgen and Symdec modules need to be fixed for validation failures Negate RESET signal in example design top Update Virtex-6 PMA_RX_CFG settings as Async protocol Remove simplex-both option from core altogether CLK25_DIVIDER_0/1 attribute values are set to 1 always for Spartan-6 VHDL version does not have correct implementation of sof generation Errors in linting Aurora 8b/10b - Spartan-6 should have possibility to use REFCLK other tile Aurora 8B/10B - Please add RXEQMIX setting to GUI and bring it to the top levelin the aurora files Aurora 8B/10B - Please add option to make DRP available at Aurora top level
The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide located at:
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