UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 45676: LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.2 - Functional simulation failure when using 1000 BASE-X and VHDL

AR# 45676

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.2 - Functional simulation failure when using 1000 BASE-X and VHDL

Description

Functional simulation failures are seen for the Ethernet 1000BASE-X PCS/PMA or SGMII version 11.2 core when the STANDARD parameter is set to 1000BASEX and VHDL design is being used for entry and simulation. 


The failures seen are:

Running functional simulation in ModelSim

Fatal: (vsim-3471) Slice range (11 downto 0) does not belong to the prefix index range (10 downto 0).
FATAL ERROR while loading design

Running functional simulation in IUS

ncelab: *E,TRINDXC: index constraint violation.
source file: GTXE2_CHANNEL.vhd, line = 1028, position = 99

Solution

To resolve this issue, on line 300 of <core_name>/example_design/transceiver/gtwizard_gt.vhd change the following:

Original:

RX_BIAS_CFG => ("00000000010"),

New:

RX_BIAS_CFG => ("000000000100"),
AR# 45676
Date 11/05/2014
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII
Page Bookmarked