AR# 45678

LogiCORE IP Initiator, Target v4.16 for PCI - When using NT machine, implement.bat may not be generated


When generating the PCI core on an NT machine, the implement.bat file may not be produced in the implement directory.


To work around this issue, another machine (Win7 or Linux) can be used to generate the core. Also, an example implement.bat is included here. This script assumes the generated core's name is pci32_v4_16. You will need to modify the script as necessary to match your generated core's name.

@echo off

rem Clean up the results directory
rmdir /S /Q results
mkdir results

rem Synthesize the Verilog wrapper files
echo Synthesizing Verilog example design with XST
xst -ifn xst.scr
copy pci32_v4_16_top.ngc results/

rem Copy the netlist generated by Coregen
echo Copying files from the netlist directory to the results directory
copy ../../pci32_v4_16.ngc results/

rem Copy the constraints file generated by Coregen
echo Copying files from constraints directory to results directory
copy ../example_design/pci32_v4_16_top.ucf results/

cd results

echo Running NGDBUILD
ngdbuild -p xc7k325t-ffg900-1 pci32_v4_16_top

echo Running MAP
map pci32_v4_16_top -o mapped.ncd

echo Running PAR
par mapped.ncd routed.ncd

echo Running TRCE
trce -e 10 routed.ncd mapped.pcf -o routed

echo Running design through BITGEN
bitgen -w routed

echo Running NETGEN to create gate-level Verilog model
netgen -ofmt verilog -sim -tm pci32_v4_16_top -w routed.ncd routed.v

Revision History
01/18/2012 - Initial Release
AR# 45678
Date 01/16/2012
Status Active
Type Known Issues