Why does the TRD notuse the MIG straightfromthe CORE Generator interface?
Why do I need modified files?
What happens when the MIG version changes and I need to update?
The Memory Controller IP core generated using the MIG tool in Core Generator does not directly support the KC705 pin layout.
mig_7x.v, the top level for the MIG core,has been modifiedto support the Kintex-7 FPGA KC705 Evaluation Kit. This file isavailable in the k7_pcie_dma_ddr3_base/design/source/modified_ip_files.mig directory of the Base TRD files.
When MIG updates in theCORE Generator software, there may be some port and parameter changes. The TRD will update this file for all the major releases starting with 13.4, so users can wait for a new ISE release to get the new MIG version integrated into the TRD.