Description

Solution

3. SUPPORTED DEVICES
 
The following device families are supported by the core for this release.

Virtex-7
Virtex-7 -2L
Virtex-7 -2G
Virtex-7 XT
Kintex-7
Kintex-7 -2L

4. RESOLVED ISSUES

   a. Modifications to Internal Datapath Width
   Description: Internal Datapath width should be 32/40 for line rate > 6.6Gbps.
   Internal Datapath width should be 20/40 for 8B/10B encoding.

   Version(s) Fixed: 
   CR 636001, 630091
   b. Modification to Reference Clock Range
   Description: Reference Clock Range for GTX is 62.5 MHz to 700 MHz for - 3 Speed Grade.
   Reference Clock Range for GTX is 62.5 MHz to 670 MHz for  all other Speed Grades.
   Reference Clock Range for GTH is 62.5 MHz to 820 MHz for  all Speed Grades.

   Version(s) Fixed: 
   CR 636216

5. KNOWN ISSUES

The following are known issues for v1.6 of this core at time of release:


 Description: This version of the core has not been validated on hardware. 

  b. Timing Simulation

 Description: Timing Simulation scripts are not generated for GTH Transceiver and PCIE protocol.

  c. Support for PCIE Gen1/Gen2 - GTX

   Description: The wrapper generated for PCIE contains instances of GTHE2 and logic specific to Gen3. Please note that both these features are under development - users are requested not to enable GTH or Gen3.

  d. Support for GTH Transceiver

   Description:
   - The number of GTs which can be selected for xc7vx1140t-flg1928 device is limited to 40.
   - Bit stream generation is not enabled for Virtex-7 XT devices.
   - Simulators Supported - MTI, IUS and VCS

The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide.

6. TECHNICAL SUPPORT

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

7. OTHER INFORMATION

This version (v1.6) of the wizard supports General ES silicon only. Use of
of this version of the core to program Initial ES devices is not supported.
Use v1.5 Rev 1 version to program Initial ES devices.

8. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
01/18/2012  Xilinx. Inc.  1.6            ISE 13.4 support
01/18/2011  Xilinx. Inc.  1.5(Rev 1) ISE 13.4 support
10/19/2011  Xilinx. Inc.  1.5            ISE 13.3 support
06/22/2011  Xilinx, Inc.  1.4            ISE 13.2 support
03/01/2011  Xilinx, Inc.  1.3            ISE 13.1 support
11/23/2010  Xilinx, Inc.  1.2            Beta 2 Release
10/29/2010  Xilinx, Inc.  1.1            Initial Release
================================================================================

Linked Answer Records

Associated Answer Records