UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable Intelligence
  2. Support
  3. AR# 45704: Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.4

AR# 45704

Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.4

Description

This article contains issues resolved in theSpartan-6 FPGA Integrated Block v2.4 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

For other known and resolved issues that may not be in this list see(Xilinx Answer 45702).

Solution

Resolved Issues

  • CR 622845: cfg_err_posted signal modification not updated in User Guide
  • CR 624052: Test selections are not updated in user guide
  • CR 624245: Figures 6-25 and 6-26 is not correctly representing transactions on the cfg_err interface
  • CR 614643: User Guide incorrectly references ACS in user guide
  • CR 624053: User Guide does not state the parity error enable bit is hardwired t1'b0
  • CR 612526: m_axis_rx_tuser bits are not fully defined in user guide
  • CR 618973: cfg_rd_en and cfg_pm_wake incorrectly listed as active low in User Guide

Revision History
01/18/2012 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45702 Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions N/A N/A
AR# 45704
Date 05/20/2012
Status Active
Type Release Notes
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )

By using this website, I accept the use of cookies.   Learn more

Page Bookmarked