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AR# 45708

LogiCORE IP Serial RapidIO Gen2 v1.3 - Release Notes and Known Issues for ISE Design Suite 13.4

Description

This Release Note and Known Issues Answer Record is for the LogiCORE Serial RapidIO Gen2 v1.3, which was released in theISE 13.4 software and contains the following information:
  • Supported Devices
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tool requirements, see the IP Release Notes Guide.

Solution

New Features

  • ISE 13.4 software support
  • Hardware validated on Kintex-7 Initial ES and Virtex-6 FPGA (see IP Release NotesGuide for more information)
  • Software assisted error recovery
  • Configurable additional link-requests before fatal
  • User-Defined port and Separate Messaging port in 5.0/6.25 Gb/s x4 configurations
  • Added Virtex-6 6.25 Gb/s x4 support
  • Added Migration Guide appendix to the Product Guide

Supported Devices

  • Virtex-7
  • Virtex-7 -2L
  • Virtex-7 -2G
  • Virtex-7 XT
  • Kintex-7
  • Kintex-7 -2L
  • Virtex-6 XC CXT/LXT/SXT/HXT

Resolved Issues

  • (Xilinx Answer 44301)LogiCORE IP Serial RapidIO Gen2 v1.2 - Asserting link_reset does not reset the core
  • (Xilinx Answer 44302) LogiCORE IP Serial RapidIO Gen2 v1.2 - LREQ-reset control symbols are not transmitted back-to-back when in IDLE2
  • (Xilinx Answer 44305)LogiCORE IP Serial RapidIO Gen2 v1.2 - Read of the Assembly Info Register returns incorrect value for assembly revision
  • (Xilinx Answer 44461) LogiCORE IP Serial RapidIO Gen2 v1.2 - Port might not initialize correctly when a cfg write causes the port to re-intialize
  • (Xilinx Answer 44718) LogiCORE IP Serial RapidIO Gen2 v1.2 - Incorrect IREQ and TRESP SourceID field connection in the example design
  • (Xilinx Answer 43482)7 Series GTX Transceivers - Reset requirements upon configuration
  • (Xilinx Answer 45488)LogiCORE IP Serial RapidIO Gen2 v1.2 - When a forced reinitialization occurs, the core does not restart the IDLE sequence selection
  • (Xilinx Answer 45490) LogiCORE IP Serial RapidIO Gen2 v1.2 - ALIGNS might not be properly detected when using the chanbondseq signal from the GTX
  • (Xilinx Answer 45492)LogiCORE IP Serial RapidIO Gen2 v1.2 - Does the core support XC7K160T-1FBG676?
  • (Xilinx Answer 45493)LogiCORE IP Serial RapidIO Gen2 v1.2 - The core does not lose sync when an invalid character is received
  • (Xilinx Answer 45494)LogiCORE IP Serial RapidIO Gen2 v1.2 - The core sends packets with overlapping ackIDs when port_init drops
  • (Xilinx Answer 45056)LogiCORE IP Serial RapidIO Gen2 v1.2 - Idle_selected signal is Hi-Z in simulation
  • (Xilinx Answer 45495) LogiCORE IP Serial RapidIO Gen2 v1.2 - The core unexpectedly trains down when ALIGN errors occur

Known Issues

  • (Xilinx Answer 45866) - LogiCORE IP Serial RapidIO Gen2 v1.3 - Malformed packet generation in the receive PHY layer
  • (Xilinx Answer 46008) - LogiCORE IP Serial RapidIO Gen2 v1.3 - 'Common Transport Large System Support' bit in Processing Elements Features CAR not set correctly
  • (Xilinx Answer 46089) - LogiCORE IP Serial RapidIO Gen2 v1.3 - Incorrect two lane port support information in "Port n Control CSR Register" table
  • (Xilinx Answer 45976) - LogiCORE IP Serial RapidIO Gen2 v1.3 - WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance....
  • (Xilinx Answer 46629) - LogiCORE IP Serial RapidIO Gen2 v1.3 - Disabling the "Source Maintenance Support" option not supported
  • (Xilinx Answer 47103) -LogiCORE IP Serial RapidIO Gen2 v1.3 - Multiple errors in close proximity can prevent core from sending out an LRESP
  • (Xilinx Answer 47019) -LogiCORE IP Serial RapidIO Gen2 v1.3 - Core loses sync when receiving clock compensation in IDLE2
  • Hardware Validation Status:
    Hardware validation for LogiCORE IP Serial RapidIO Gen2 v1.3 is currently in progress. For the current validation status, please contact Xilinx Technical Support by opening a WebCase at: http://www.xilinx.com/support/clearexpress/websupport.htm

Resolved Issues in v1.3 Rev1

  • (Xilinx Answer 46904)LogiCORE IP Serial RapidIO Gen2 v1.3 - Core sends out a PNA when receiving control symbols separated by less than 4 idle bytes
  • (Xilinx Answer 46905)LogiCORE IP Serial RapidIO Gen2 v1.3 - treq_tvalid togglescontinuously when treq_tready is de-asserted in the middle of data transfer

Download Rev1 Update

To install the v1.3 rev1 update, apply the following patch to the Xilinx ISE 13.4 installation:
http://www.xilinx.com/txpatches/pub/swhelp/ise13_updates/ar45708_srio_gen2_v1_3_rev1_preliminary.zip

Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE 13.4 installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

After installing the patch, regenerate the LogiCORE IP Serial RapidIO Gen 2 v1.3 in the CORE Generator tool. For more information on finding the Xilinx installation and using environment variables, see (Xilinx Answer 11630).

NOTE:You might need system administrator privileges to install the patch if you do not have write permissions to the Xilinx installation directory.

Revision History
04/05/2012 Added links to Answer Records 47103 and 47019
03/21/2012 Added Rev1 Patch and links to Answer Records 46904 and 46905
02/03/2012 Added link to Answer Record 45976
01/31/2012 Added link to Answer Record 46089
01/27/2012 Added link to Answer Record 46008
01/19/2012 Added link to Answer Record 45866
01/18/2012 Initial Release

AR# 45708
Date Created 01/06/2012
Last Updated 05/16/2012
Status Active
Type Release Notes
IP
  • Serial RapidIO