AR# 45717: MIG 7 Series DDR3 - Multi-Controller designs fail to generate in MIG
MIG 7 Series DDR3 - Multi-Controller designs fail to generate in MIG
When generating a MIG 7 Series DDR3 Multi-Controller design, the MIG tool will not proceed past the Bank Selection page or System Signals Selection page. These are valid scenarios but MIG is not providing valid messages to guide the user. This answer record goes through these scenarios and provides steps for the user to proceed.
Various scenarios are as follows:
If the selected target device is too small to fit the selected number of controllers, user cannot generate the design. User cannot proceed past the "Bank Selection" Page. In such cases, users need to target a larger FPGA device.
It is possible that with optimum banks selections, a specific number of controllers can fit into a specific part. However, if a user selects sub-optimum bank/pin selections, the controllers may no longer fit and the user cannot proceed further in the "Bank Selection" Page. In such cases, the user needs to target a larger FPGA device or needs to use the optimum bank selections.
System clock and Reference clock pins can be selected for CC_P/CC_N I/O pins only. If user selected banks/pins for various controllers such that there are no CC_P/CC_N pins available for selection of system clock and reference clock pins, the user cannot select pins for system clock and reference clock pins. Users can select the option for status signals as "No Connect" and can proceed in design generation.
"Status Signals" are not allowed in memory interface signal banks because the IOSTANDARD of status signals are different from the memory interface signal's voltage standard. If the banks are selected for memory interface signals such that there are no banks available for "Status Signals," users cannot proceed in design generation. To work around this select the option for status signals as "No Connect" and proceed in design generation.