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AR# 45723

Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions

Description

This Release Notes and Known Issues answer record is for the AXI Interface version of the Virtex-6 FPGA Integrated Block for PCI Express that was first released in ISE Design Suite 12.3.

Solution

For installation instructions, general CORE Generator tools known issues, and design tools requirements, see the IP Release Notes Guide.


General Information

 

New Features

  • ISE 13.4 design tools

Supported Devices

  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT

Note: For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Known Issues

This table correlates the core version to the first ISE design tools release version in which it was included.

Core Version
ISE Version
v2.5
ISE 13.4
v2.4
ISE 13.2
v2.3
ISE 13.1
v2.2
ISE 12.4
v2.1
ISE 12.3

The following table provides known issues for the AXI interface version of the Virtex-6 FPGA Integrated Block for PCI Express.

Note: The "Version Found" column lists the version the problem was first discovered. The problem can also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Article Number
Article Title
Version Found
Version Resolved
(Xilinx Answer 60418) The core may truncate some DLLPs/TLPs during the process of going into Recovery v2.5 Not Resolved Yet
(Xilinx Answer 51871)
Missing MRds following PCIe hot reset v2.5  Not Resolved Yet
(Xilinx Answer 57345) Bus/Device/Function Number Change Upon Configuration Type 1 Accesses v2.5 Not Resolved Yet
(Xilinx Answer 53459) Incorrect VSEC_BASE_PTR value when Extended Capabilities DSN and VSEC are enabled v2.5 Not Resolved Yet
(Xilinx Answer 47280) Timing fails due to missing Block RAM Placement (LOC) Constraints in the Example Design UCF v2.5 Not Resolved Yet
(Xilinx Answer 46793)
A timing constraint for x8 gen2 (ML605) is incorrect
v2.5
Not Resolved Yet
(Xilinx Answer 37784)
x8 Gen 2 Timing Closure
v2.1
Not Resolved Yet
(Xilinx Answer 45771)
The receive interface signal m_axis_rx_tvalid might deassert in the middle of a packet when using the 128-bit x8 Gen 2 interface
v2.1
Not Resolved Yet
(Xilinx Answer 45733)
List of other issues resolved in v2.5
v2.5
2.5
(Xilinx Answer 43531)
When simulating a VHDL x8 Root Port, the example design does not link up until around 122 micro-seconds.
v2.3
2.4
(Xilinx Answer 40464)
PIO_RX_ENGINE.vhd does not accept 64-bit addressable memory writes
v2.1
2.4
(Xilinx Answer 40466)
m_axis_rx_tstrb[7:0] only outputs 0x0F
v2.2
2.4
(Xilinx Answer 41051)
x8 Gen 2 128-bit transmit interface might drop single cycle packets
v2.3
2.4
(Xilinx Answer 41509)
MSI-X Table Size Field in Customization GUI should be entered as decimal number
v2.3
2.4
(Xilinx Answer 42756)
List of other issues resolved in v2.4
v2.4
2.4
(Xilinx Answer 40637)
DRC Error During Simulation using Provided Root Port Model
v2.2
2.3
(Xilinx Answer 39456)
Link Training Issues due to Delay Aligner
v2.2
2.3
(Xilinx Answer 39656)
Clock net TxOutClk_bufg is not constrained
v2.2
2.3
(Xilinx Answer 39544)
Asynchronous Links Should Change PMA_RX_CFG
v2.2
2.3
(Xilinx Answer 40445)
List of other issues resolved in v2.3
v2.3
2.3
(Xilinx Answer 39164)
Need to set BANDWIDTH attribute on MMCM to Low
v2.1
v2.2
(Xilinx Answer 38223)
Disabling Legacy Interrupts in the GUI does not change Interrupt Pin register
v2.1
v2.2
(Xilinx Answer 39353)
List of other issues resolved in v2.2
v2.2
2.2
(Xilinx Answer 34009)
Link Training on ML605 Boards with ES silicon
v2.1
2.1
(Xilinx Answer 37937)
List of other issues resolved in v2.1
v2.1
2.1
(Xilinx Answer 37963)
VHDL Wrapper Not Available for v2.1 Release
v2.1
v2.2

 

Revision History

29/04/2014 - Added (Xilinx Answer 60418)
09/06/2013 - Added (Xilinx Answer 57345) and (Xilinx Answer 51871)
12/17/2012 - Added (Xilinx Answer 53459)
09/03/2012 - Added (Xilinx Answer 47280)
07/06/2012 - Added (Xilinx Answer 46793)
02/02/2012 - Added (Xilinx Answer 45771)
01/18/2012 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
45733 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.5 N/A N/A
43531 Virtex-6 FPGA Integrated Block for PCI Express - When I simulate a VHDL x8 Root Port, the example design does not link up until around 122 microseconds N/A N/A
42756 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.4 N/A N/A
41509 Virtex-6 Integrated Block for PCI Epxress - MSI-X Table Size field in customization GUI should be entered as decimal number N/A N/A
41051 Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 128-bit Transmit Interface May Drop Single Cycle Packets N/A N/A
40466 Virtex-6 FPGA Integrated Block Wrapper v2.3 for PCI Express (AXI) - m_axis_rx_tstrb[7:0] only outputs 0x0F N/A N/A
40464 Virtex-6 FPGA Integrated Block for PCI Express - PIO_RX_ENGINE.vhd does not accept 64-bit addressable memory writes N/A N/A
40445 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.3 N/A N/A
39656 Viretx-6 FPGA Integrated Block for PCI Express - Clock net TxOutClk_bufg is not constrained N/A N/A
39544 Virtex-6 FPGA Integrated Block for PCI Express (AXI) - Asynchronous Links Should Change PMA_RX_CFG N/A N/A
39353 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2 N/A N/A
39164 Design Advisory for the Virtex-6 Integrated Block for PCI Express - Need to set BANDWIDTH attribute on MMCM to Low N/A N/A
38223 Virtex-6 Integrated Block for PCI Express - Disabling Legacy Interrupts in the GUI does not change Interrupt Pin register N/A N/A
37963 Virtex-6 FPGA Integrated Block for PCI Express - VHDL Wrapper Not Available for v2.1 Release N/A N/A
37937 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.1 N/A N/A
37784 Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 Timing Closure N/A N/A
34009 Virtex-6 Integrated Block Wrapper for PCI Express- PCI Express link will not train on ML605 boards using ES silicon N/A N/A
45771 Design Advisory for the Virtex-6 Integrated Block for PCI Express - The receive interface signal m_axis_rx_tvalid might deassert in the middle of a packet when using the 128-bit x8 Gen 2 interface N/A N/A
39456 Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Delay Aligner Workaround N/A N/A
47280 Virtex-6 Integrated Block for PCI Express v2.5 - Timing fails due to missing Block RAM Placement (LOC) Constraints in the Example Design UCF N/A N/A
57345 Virtex-6 Integrated Block for PCI Express v2.5 - Bus/Device/Function Number Change Upon Configuration Type 1 Accesses N/A N/A
AR# 45723
Date Created 01/09/2012
Last Updated 04/29/2014
Status Active
Type Release Notes
IP
  • PCI-Express (PCIe)