There is an issue with the FIR Compiler v6.3 where if the ACLKEN to the core is set at configuration to '0' and ARESETn is not used, then, even though theACLKENis driven High, the output from the FIR Compiler is at zero.
This answer record contains a patch update for theLogiCOREIP FIR Compilerv6.3 tofix this issuewhere the Clock Enable on FIR Compiler cannot be set to a '0' from startup.
TheFIR Compilerv6.3 patch can be downloaded at:
Installation and Use
Prior to installing the update, you must install the latest ISE Design Suite release of13.4 as required by the patch. If needed, the ISE Design Suite release can be obtained from the following link: http://www.xilinx.com/support/download/index.htm.
Install the patch by extracting the contents of the ZIP archive to the root directory of XILINX (Xilinx ISE software installation), or your MYXILINX environment variable. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.
For information on finding the Xilinx install and using the environment variable, see (Xilinx Answer 11630).
For information on using the MYXILINX environment variable, see (Xilinx Answer 2493).
NOTE: If you do not have write permissions to the Xilinx Install directory, or cannot use the MYXILINX option, you might be required to have a system administrator install the patch.
You can determine if the patch has been properly installed by checking to see if RevX (where X is the patch number) is listed in the Description field, when the core is selected in the CORE Generator tool.
Within System Generator, it will be necessary to clear the cache. Please use the following command:
For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).