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  3. AR# 4576: ngd2edif: ERROR: Baspm:19 - Unable to open Xilinx Data file ..."viewlog"
  4. AR# 45761: 13.4 Map: ERROR:PhysDesignRules:2379 - Issue with pin connections and/or configuration

AR# 45761

13.4 Map: ERROR:PhysDesignRules:2379 - Issue with pin connections and/or configuration

Description

I am seeing the following error during MAP for a Virtex-7 device. What is the reason behind this and how should I fix this?

ERROR:PhysDesignRules:2379 - Issue with pin connections and/or configuration on block:edradour_top/pdhdmap/e1t1rx/deframer/t1_logic/ff_ram_ram/ix60576z19871. The cascadable BlockRam feature is not used for port B (RAM_EXTENSION_B set to NONE). The highest order port B address bit (ADDRBWRADDRL15) must be tied to LOGIC 1.

Solution

This is a valid DRC error . The address bit 15 is only used in cascadable block RAM. The valid addresses for non-cascadable block RAM are only found on pin 14 to (15 - address width). The remaining pins , including pin 15, should be tied High. Please refer page 29 and 37 of the following user guidetofind more information on the DRC.

http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

AR# 45761
Date 12/15/2012
Status Active
Type General Article
Devices
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