AR# 45765

MIG v3.91 Virtex-6 DDR3/DDR2 - 72-bit and 144-bit AXI Lite designs fail in simulation using ModelSim

Description

MIG v3.91 Virtex-6 DDR3/DDR2 72-bit and 144-bit AXI Lite designs may fail in simulation with a segmentation fault when using ModelSim.

Solution

This onlyaffects Virtex-6 DDR3/DDR2 AXI Lite 72-bit and 144-bit designs, but can be worked around by replacing the "-novopt" command with "-voptargs="+acc"" in the sim.do file located in the ./sim directory, or the user can use ISE Simulator.

This issue will be fixed in a future version of ModelSim.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45194 MIG Virtex-6 and Spartan-6 v3.91 - Release Notes and Known Issues for ISE Design Suite 13.4 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45194 MIG Virtex-6 and Spartan-6 v3.91 - Release Notes and Known Issues for ISE Design Suite 13.4 N/A N/A
AR# 45765
Date 07/02/2012
Status Active
Type Known Issues
Devices
IP