AR# 45810

AutoESL - Integration of AutoESL Design with AP_FIFO and AXI_Stream Interface into System Generator using Blackbox Flow


The attached reference design is intended to show a possible flow to integrate VHDL and Verilog code generated with the AutoESL tool from a C source into a System Generator design using the Blackbox flow.

The System Generator design contains a SysGen FFT block v8.0 using the AXI-Stream interface. A simple peak search module has been written in C and synthesized with AutoESL with two different interfaces:

  • peak_search module with AP_FIFO interface
  • peak_search module with AXI_Stream interface

The SysGen design incorporates both HDL modules using the HDL Blackbox flow. The peak search modules determine the maximum power value of the frequency spectrum (FFT result) and its frequency index and output both values.

Design Languages (HDL/SW): System Generator, AutoESL


Design Reference Document

The attached ZIP file contains the System Generator model and both AutoESL projects including the generated Verilog and VHDL files.
The C souce has been synthesized with AutoESL (project C_AP_FIFO/proj_peak_search) using the directive:

set_directive_interface -mode ap_fifo "peak_search" data_in

to generate an AP_FIFO interface to connect to the FFT block within SysGen.

In a second AutoESL project (C_AXI_STREAM/proj_peak_search_axis), the same C source code has been slightly modified to allow the generation of an AXI_Stream interface. The following lines have been added:

#include "ap_interfaces.h"
#include "ap_axi_sdata.h"

The design needs to be implemented within AutoESL after HL synthesis to generate a pcore which contains a wrapper file with the AXI_Stream interface adapter (directory C_AXI_STREAM\proj_peak_search_axis\solution1_axi_stream\impl\pcores\peak_search_top_v1_00_a\synhdl\verilog). All of the files contained in this directory, along with the *.v and *.dat files generated within directory C_AXI_STREAM\proj_peak_search_axis\solution1_axi_stream\impl\verilog need to be copied to an include directory within the SysGen design (SysGen\verilog_peak_search_axi_stream), since they need to be added to the Matlab setup script for the Blackbox modules (SysGen\peak_search_top_wrap_config.m). AutoESL currently only allows generation of Verilog HDL code for AXI_Stream interface support. A CR has been filed to get the support for VHDL as well.

A Verilog wrapper file has been written to comply with all System Generator blackbox module restrictions:

  • clk and ce port names (clock enable port ce is not connected in this example)
  • connection of both clock ports (AXI Stream IF clock and SYS_CLK) to a single top level wrapper clock port
  • lower case letters for port names.

The necessary connections between the FFT block AXI_Stream IF and the AutoESL blackbox modules using AP_FIFO and AXI_Stream interfaces can be reviewed within the System Generator design module. Simulation within System Generator shows that both AutoESL generated HDL designs generate the same (expected) results.

The following screenshot shows the System Generator design, containing the FFT block and both AutoESL generated modules, incorporated as lackboxes.


Associated Attachments

Name File Size File Type 2 MB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 45810
Date 03/02/2013
Status Active
Type General Article
Tools More Less