When users select two different reference clock sources for a single dual, the reference clock connections in the wrapper files are wrong. However, the tools automatically connect them to the correct ports.
For example, when REFCLK0 XOY1 is selected for GTP0 REFCLK and REFCLK1 X0Y1 is selected for GTP1 REFCLK in the Wizard, according to figure 2-2 of the Spartan-6 FPGA GTP Transceivers User Guide (UG386), REFCLK1 should be connected to either CLK10 or CLK11, but the generated s6_gtp_sample.vhd (line 381, 382) connects REFCLK1 to CLK01 which is incorrect. The tools automatically connect it to CLK11 and this can be confirmed by FPGA editor.
| AR# 45861 | |
|---|---|
| Date | 06/06/2017 |
| Status | Archive |
| Type | General Article |
| Devices | |
| IP | |