AR# 45863: PlanAhead - Error while open_netlist_design when ILA core is instantiated in RTL after setup ChipScope Wizard
PlanAhead - Error while open_netlist_design when ILA core is instantiated in RTL after setup ChipScope Wizard
The below error is received in PlanAhead when an ILA core is instantiated in RTL after the setup ChipScope wizards:
ERROR: [Netlist-7] Could not replace (cell 'icon', library 'icon_lib', file 'icon.ngc') with (cell 'i_chipscope_icon_v1_05_a_0_CV', library 'i_chipscope_icon_v1_05_a_0_lib', file 'i_chipscope_icon_v1_05_a_0.ngc') because of a port interface mismatch; Port 'CONTROL2' is missing on the replacing cell.
The icon core in the ChipScope core cache is invalid.
This is because the HDL icon core has changed but the cache does not get invalidated.
The result is that a 2 port icon core is read from the cache and applied to the netlist where a 3 port icon core is required.
This issue is fixed in Vivado Design Suite from the first public version on.
To work around the issue in PlanAhead follow the steps below:
Edit the chipscope.xml file in the <project>.data/sources_1 directory.
Locate the "chipscope_icon_v1" core type in the xml file.
Remove the srcNetlist, srcXdc, and srcNcf entries from the coreStatus entry.
This will force the icon core to black box instead of reading from the cache.