The below error is received in PlanAhead when an ILA core is instantiated in RTL after the setup ChipScope wizards:
The icon core in the ChipScope core cache is invalid.
This is because the HDL icon core has changed but the cache does not get invalidated.
The result is that a 2 port icon core is read from the cache and applied to the netlist where a 3 port icon core is required.
This issue is fixed in Vivado Design Suite from the first public version on.
To work around the issue in PlanAhead follow the steps below:
This will force the icon core to black box instead of reading from the cache.