General Description: FPGA Express 2.x (or Foundation F1.5 or F1.5i) ignore instantiations of SRL (Shift Register LUTs) for Virtex designs. These components are SRL16, SRL16E, SRL16_1, and SRL16E_1.
This problem has been fixed with FPGA Express 3.0. Alliance users should download this version from the Synopsys FTP site.
For Foundation, Express 3.1 is available in Service Pack 1 for F1.5i. See (Xilinx Solution 5631) for details on downloading and installing this upgrade.
For users unable to upgrade to Express 3.x, the workaround is to create a macro in a Foundation schematic and instantiate this macro as a black box. Follow these steps:
1. Ensure the Virtex library is defined in your HDL project. If the Virtex library is not listed in the Files tab of your Foundation project, select File -> Project Libraries. Select "virtex" under "Attached Libraries" and click on the Add button, then click on the Close button.
2. Open the schematic editor. Create a schematic that contains only the Shift Register LUT that you wish to use (or more components, if you wish). Complete the schematic by attaching nets to all the pins you wish to use. Use I/O terminals and labels to define the I/O of this macro.
The schematic will look like the following:
Figure 1- SRL16 macro schematic
3. Use File -> Save As to save this schematic with a unique name. DO NOT use the same name as one of the SRL macros (or any other library name) and do not use the name of the project.
4. Select Options -> Create Netlist from Current Sheet to write the netlist (an .ALB file).
5. Select Options -> Export Netlist. Make sure the .ALB file listed matches the schematic you have created. DO NOT change directories; save this .EDN file in the current Foundation Project. Click Open to save.
6. Close the schematic editor. Note that the schematic does not show up in the Files tab. Do not add the schematic or .EDN file to this project. Because this macro is to be instantiated as a black box, Express must have no knowledge of the contents of this macro.
7. Instantiate the macro in your HDL code. Use the names of the I/O terminals in the schematic as the port names in your HDL instantiation.
8. Because the .EDN file exists in the project directory, the Translate phase of Implementation will merge this macro with your top-level design. If you would like to use this macro in other designs, simply copy the .EDN file to other project directory.