2. Support
  3. AR# 4588: FPGA Express 2.x: Express ignores SRL instantiations for Virtex designs.
  4. AR# 45889: Project Navigator - Setting Project Property in Tcl shell flags results in a parsing error that is not shown in the GUI

AR# 45889

Project Navigator - Setting Project Property in Tcl shell flags results in a parsing error that is not shown in the GUI

Description

When running a Tcl script to set some project properties and run bitgen,I see a parsing syntax error or errors.

However, I do not see the errors if I set the same properties in the GUI.

Is there a reason why I would see this behavior.

Solution

This situation will occur if there aresyntax errors between translate_off and translate_on statements in the HDL file.

Setting a property (successfully or not) causes a re-parse of the project sources.

The re-parse is actually done twice, once for synthesis, and once for simulation. If the filewith the syntax erroris marked as available for simulation, orimplementation and simulation, the simulation parse will flag the syntax error(s) between thetranslate_off and translate_on statements.

For Implementation, these errors can be ignored, or the file in question can be marked for implementation only. However, the syntax should be corrected before simulation is run.
AR# 45889
Date 12/15/2012
Status Active
Type General Article
Tools