AR# 45915

Description

When using the Local Link FIFO provided in the Tri-Mode Ethernet MAC v4.5 and earlier example design and operating at 10Mb/s or 100Mb/s, it is possible for the FIFO to not clear correctly when a reset is issued in the middle of a write to the FIFO.

Solution

To resolve this issue, change reg_eof_p in the file rx_client_fifo.v/vhd to add a reset.

VHDL:

Starting on line 784 of example_design/fifo/rx_client_fifo.vhd change:

 reg_eof_p : process(wr_clk)
  begin
    if (wr_clk'event and wr_clk = '1') then
        if wr_enable = '1' then
           wr_dv_pipe(0) <= rx_data_valid;
           wr_dv_pipe(1) <= wr_dv_pipe(0);
           wr_eof_bram(0) <= wr_dv_pipe(1) and not wr_dv_pipe(0);
        end if;
     end if;
  end process reg_eof_p;

To:

reg_eof_p : process(wr_clk)
  begin
     if (wr_clk'event and wr_clk = '1') then
        if wr_sreset = '1' then
           wr_dv_pipe    <= (others => '0');
           wr_eof_bram   <= (others => '0');
        elsif wr_enable = '1' then
           wr_dv_pipe(0) <= rx_data_valid;
           wr_dv_pipe(1) <= wr_dv_pipe(0);
           wr_eof_bram(0) <= wr_dv_pipe(1) and not wr_dv_pipe(0);
        end if;
     end if;
  end process reg_eof_p;

Verilog:

Starting on line 771 of example_design/fifo/rx_client_fifo.v change:

  always @(posedge wr_clk)
  begin
     if (wr_enable == 1'b1) begin
        wr_dv_pipe[0] <= rx_data_valid;
        wr_dv_pipe[1] <= wr_dv_pipe[0];
        wr_eof_bram[0] <= wr_dv_pipe[1] & !wr_dv_pipe[0];
     end
  end

 To:

  always @(posedge wr_clk)
  begin
    if (wr_sreset == 1'b1) begin
      wr_dv_pipe[0] <= 1'b0;
      wr_dv_pipe[1] <=1'b0;
      wr_eof_bram <= 1'b0;
    
    end
    else if (wr_enable == 1'b1) begin
        wr_dv_pipe[0] <= rx_data_valid;
        wr_dv_pipe[1] <= wr_dv_pipe[0];
        wr_eof_bram[0] <= wr_dv_pipe[1] & !wr_dv_pipe[0];
     end
  end