Version Found: v1.4
Version Resolved and other Known Issues: See(Xilinx Answer 45195).
Dual Rank DDR2/DDR3 cores generated with the ISE 13.4 MIG 7 Series v1.4 release should notbe implemented in hardware. This applies to both dual rank DIMMs and twin or dual die configurations in a single package.
The pinouts generated by MIG 7 Series v1.4 should also not be used for pin planning of dual rank designs as it is likely to change going forward. The RTL can still be simulated for general understanding of the core functionality.
Hardware support for dual rank designs was previously targeted for 14.1, but has now been set for the 14.2 release. Dual rank designs have been completely removed from the 14.1 release to prevent any invalid pinouts and RTL from being used.
05/08/2012 - Updated release schedule to 14.2
03/12/2012 - Removed pin planning support