AR# 4599

4.2i Foundation - State Editor generates incorrect one-hot encoded VHDL with a trap state exit logic

Description

Keywords: Foundation, State Editor, one-hot, state machine, VHDL, generate, FSM, trap, illegal, state

Urgency: Standard

General Description:
When I generate VHDL code from State Editor to implement a one-hot encoded FSM with trap state exit logic, the simulation shows that the transition from illegal states to the trap state does not work.

FSM goes to the proper trap state when reset is asserted, but logic, rather than a reset signal, should force an exit from any illegal states on the next clock transition.

Solution

1

The FSM must be synthesized with the following option checked: "Safest - All possible, including illegal, states".

In Foundation Project Manager, go to Synthesis -> Options. Under "FSM Synthesis", check "Safest (All possible, including illegal, states)".

2

To work around this problem, edit the VHDL code to explicitly list all the enumerated states. (However, this will be quite cumbersome if you have large state machines.)
AR# 4599
Date 08/12/2003
Status Archive
Type General Article