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  3. AR# 4599: 4.2i Foundation - State Editor generates incorrect one-hot encoded VHDL with a trap state exit logic
  4. AR# 45990: RTL Technology Viewer - Bus indexes are always shown with parenthesis

AR# 45990

RTL Technology Viewer - Bus indexes are always shown with parenthesis

Description

I can alter the generated bus delimiter for signals output in an NGC file using thebus_delimiter option of XST. However, in the Technology View schematic, the signal names are always shown with parenthesis.

For example, if the bus delimiter option is set to angle brackets, the NGC might have nets similar to "19:OUTPUT:out1<18:0>", but the Technology Viewer schematic will show the net as "out1(18:0)".

Solution

The RTL/Technology viewers are built based on the ISE Schematic Capture code base. This parenthesis notation is a product of the Schematic Capture representation of a bus. Although a bus is represented in the Technology view with parenthesis, the bus_delimiter option is properly passed and used by XST synthesis.
AR# 45990
Date 12/15/2012
Status Archive
Type General Article
Tools