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AR# 45991

13.3 Project Navigator - Incomplete project hierarchy sent to XST when project contains mixed language IP Core


If the CORE Generator tooldelivers source code to Project Navigator with a mix of VHDL and Verilog source, XST might not elaborate the design hierarchy which leads to a warning in XST and a failure in NGDBuild. The failure seems to be related to the order thatthe IP core is added to the project relative to other files.

This issue has been seen with the AXI VDMA v3.1 core that delivers a mix of Verilog and VHDL source files.


This problem is specific to Spartan-6, Virtex-6 and Virtex-7 FPGA projects where the VHDL sources of an IP core are compiled into a library other than work.

Two possible ways to work around this issue are:

  • Set the XST synthesis property 'Library for Verilog Sources' to match the vhdl library for the core.
  • Setting the verilog include path (-vlgincdir ) to the IP core HDL source directory will cause XST to synthesize and elaborate the hierarchy properly.

In software version 13.4, Project Navigator allows the 'verilog lib' to be set to 'autogenerate'. When this option is set, Project Navigatorattempts to figure out what the verilog libraries should be. However, it is not able to correctly determine the libraries in all cases.

The AXI VDMA v5.0 has been re-written to only include a single HDL language.

AR# 45991
Date 05/19/2012
Status Active
Type Known Issues
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3