In order to set the CDR PI phase, please set the ports as follows:
RXCDRHOLD = 1'b0
RXCDROVRDEN = 1'b1
The PI phase is driven by 7 bits of RXCDR_CFG parameter.
The PI can vary the output phase with 128 steps spanning the VCO period (two UI due to DDR).
For IES silicon:
RXCDR_CFG[36:30]
For GES silicon:
RXCDR_CFG[15:9] The DRP address hex is 0A8[15:9]
In changing the phase, never jump more than 8 positions per update.
| AR# 46024 | |
|---|---|
| Date | 02/28/2013 |
| Status | Active |
| Type | General Article |
| Devices |
|