AR# 46044


Design Advisory for LogiCORE IP AXI VDMA - Incorrect TIG Propagation in EDK


There is a known issue in theEDK flow forAXI VDMA v5.00.a designs which usetheasynchronousclock mode,but each clock is not completelyindependent from each other.

When the VDMA is in 'Synchronous' mode, all the VDMA clocks are the same. However, in 'Asynchronous' mode (C_PRMRY_IS_ACLK_ASYNC=1), the user is responsible for providing all ofthe necessary clocks.

It wasassumed thatwhen in 'Asynchronous' mode the customer would be using all different clocks. Thus, a series ofFROM-TO TIGs were added to the core for false paths between these different clock domains. However, if the same clock signalfor two or more of the AXIVDMA clock ports is used, the FROM-TO TIGs will incorrectly constrain all paths inthat single clock domain. The result is that all legitimate timing errors in that clock domain are suppressed, resulting in a (likely) erroneous timing score. The design will not be placed/routed properly because of this incorrectly timed core. This will manifest itself differently in each design as modules outside of the AXI VDMA which run off of one of these shared clocks can fail. In general, watch out for timing related issues.

Following is an example timing report from an incorrectly constrained AXI VDMA core:

Timing constraint: PATH

"TS_axi_vdma_0_from_s_axis_s2mm_aclk_to_m_axi_s2mm_aclk_path" TIG;

182402 paths analyzed, 58454 endpoints analyzed, 0 failing endpoints

0 timing errors detected. (0 setup errors, 0 hold errors)


This work-around is not needed if:

  • All clocks are synchronous (C_PRMRY_IS_ACLK_ASYNC=0), or
  • All clocks are asynchronous(C_PRMRY_IS_ACLK_ASYNC=1) and connected to different clock sources.

However,the following work-around must be applied if:

  • All clocks are asynchronous(C_PRMRY_IS_ACLK_ASYNC=1) and some of the clocks are connected to the same clock source.

To work around this issue, make the AXI VDMA core local and edit the tcl script to remove allerroneous FROM-TO TIGs under the 'prmry_is_async' section.

  1. Make the pcore local to the XPS project; right-click on the core instance, select Make ThisIP Local.
  2. Navigate to thepcores/axi_vdma_v5_00_a_axi_datamover_v3_00_a/data directory.
  3. Open theaxi_vdma_v5_00_a_axi_datamover_v2_1_0.mpd file.
  4. Edit line 55 to replaceBEGIN axi_datamover with BEGINaxi_vdma_v5_00_a_axi_datamover.
  5. Save the file.
  6. Navigate to the pcores/axi_vdma_v5_00_a/data/ directory.
  7. Open the axi_vdma_2_1_0.tcl file.
  8. Comment out anylines from77 to 136 in the tcl file which incorrectly constrain signals inthe same clock domain. For example, if the core is set to asynchronous mode(C_PRMRY_IS_ACLK_ASYNC=1)and m_axi_mm2s_aclk and s_axi_lite_aclk use the same clock source, comment out the following TIGs:

    puts $outputFile "TIMESPEC TS_${instname}_from_s_axi_lite_aclk_to_m_axi_mm2s_aclk = FROM \"s_axi_lite_aclk\" TO \"m_axi_mm2s_aclk\" TIG;"
    puts $outputFile "TIMESPEC TS_${instname}_from_m_axi_mm2s_aclk_to_s_axi_lite_aclk = FROM \"m_axi_mm2s_aclk\" TO \"s_axi_lite_aclk\" TIG;"
  9. Save the file.
  10. In XPS, select Project and click Rescan User Repositories.

This issue is planned to be fixed starting in EDK 14.1.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
46117 Design Advisory Master Answer Record for LogiCORE IP AXI VDMA N/A N/A
47654 AXI Video Direct Memory Access (VDMA) - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46117 Design Advisory Master Answer Record for LogiCORE IP AXI VDMA N/A N/A
AR# 46044
Date 10/18/2012
Status Active
Type Design Advisory
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