There is a known issue in theEDK flow forAXI VDMA v5.00.a designs which usetheasynchronousclock mode,but each clock is not completelyindependent from each other.
When the VDMA is in 'Synchronous' mode, all the VDMA clocks are the same. However, in 'Asynchronous' mode (C_PRMRY_IS_ACLK_ASYNC=1), the user is responsible for providing all ofthe necessary clocks.
It wasassumed thatwhen in 'Asynchronous' mode the customer would be using all different clocks. Thus, a series ofFROM-TO TIGs were added to the core for false paths between these different clock domains. However, if the same clock signalfor two or more of the AXIVDMA clock ports is used, the FROM-TO TIGs will incorrectly constrain all paths inthat single clock domain. The result is that all legitimate timing errors in that clock domain are suppressed, resulting in a (likely) erroneous timing score. The design will not be placed/routed properly because of this incorrectly timed core. This will manifest itself differently in each design as modules outside of the AXI VDMA which run off of one of these shared clocks can fail. In general, watch out for timing related issues.
Following is an example timing report from an incorrectly constrained AXI VDMA core:
Timing constraint: PATH
182402 paths analyzed, 58454 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
This work-around is not needed if:
However,the following work-around must be applied if:
To work around this issue, make the AXI VDMA core local and edit the tcl script to remove allerroneous FROM-TO TIGs under the 'prmry_is_async' section.
This issue is planned to be fixed starting in EDK 14.1.