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AR# 46053

LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) v2.2 - Kintex-7 FPGA example design does not place

Description

When using the Ten Gigabit Ethernet PCS/PMA v2.2 core to target Kintex-7 devices, implementation errors out during place due to a BUFR being used to drive the GTX DRP clock.

It is not possible to route from a BUFR to GTX in the Kintex-7 device. 

The following error occurs:

ERROR:Place:1459 - Regional Clock Net "dclk" cannot possibly be routed to component"ten_gig_eth_pcs_pma_block/gtwizard_10gbaser_i/gt0_GTWIZARD_10GBASER_i/gtxe2_ i" (placed in clock region"CLOCKREGIONP_X1Y3"), since it is too far away from source BUFR "ten_gig_eth_pcs_pma_block/gt0_usrclk_source/bufr_inst" (placed in clock region "CLOCKREGION_X0Y3"). For this clock net to be routable, the clock source and all loads should be in the same cloc k region. The situation may be caused byuser constraints, or the complexity of the design. Constraining the component s related to the regional clock properlymay guide the tool to find a solution. To debug your design with partially routed results, please allow map/placer t o finish the execution (by settingenvironment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

Solution

The BUFR used to generate the divided down DRPCLK must be replaced with an MMCM with a BUFG at the output. 

The following changes should be made to the example design:

For Verilog

1) Modify the example_design/<core_name>_block.v file to add in the MMCM:

a) Add the below clock module

CLOCK_MODULE #(
.MULT(4),
.DIVIDE(1),
.CLK_PERIOD(6.4),
.OUT0_DIVIDE(8),
.OUT1_DIVIDE(1),
.OUT2_DIVIDE(1),
.OUT3_DIVIDE(1)
) dclk_divider
(// Clock in ports
.CLK_IN(clk156),
// Clock out ports
.CLK0_OUT(gt0_drpclk_i),
.CLK1_OUT(),
.CLK2_OUT(),
.CLK3_OUT(),
// Status and control signals
.MMCM_RESET_IN(tied_to_ground_i),
.MMCM_LOCKED_OUT()
);

b) Comment out the current GT_USRCLK_SOURCE file and replace it with the following:

GT_USRCLK_SOURCE gt_usrclk_source
(
.Q1_CLK0_GTREFCLK_PAD_N_IN (Q1_CLK0_GTREFCLK_PAD_N_IN),
.Q1_CLK0_GTREFCLK_PAD_P_IN (Q1_CLK0_GTREFCLK_PAD_P_IN),
.Q1_CLK0_GTREFCLK_OUT (q1_clk0_refclk_i),

.GT0_TXUSRCLK_OUT (gt0_txusrclk_i),
.GT0_TXUSRCLK2_OUT (gt0_txusrclk2_i),
.GT0_TXOUTCLK_IN (gt0_txoutclk_i),
.GT0_RXUSRCLK_OUT (gt0_rxusrclk_i),
.GT0_RXUSRCLK2_OUT (gt0_rxusrclk2_i),
.GT0_RXOUTCLK_IN (gt0_rxoutclk_i),
.DRPCLK_IN (tied_to_ground_i),
.DRPCLK_OUT()
);

2) In example_design/gtx/gt_userclk_source.v comment out the BUFR:

//BUFR
// #(
// .BUFR_DIVIDE("2")
// )
// (
// .I (q1_clk0_gtrefclk),
// .CE (tied_to_vcc_i),
// .CLR (tied_to_ground_i),
// .O (DRPCLK_OUT)
// );

3) In example_design/gtx/clock_module.v add a BUFG to the feedback path and connect the input and output ports to the MMCM CLKFBOUT and CLKFBIN ports:

wire clkfbout_bufg;

...

.CLKFBIN (clkfbout_bufg),

...

BUFG clkfb_bufg
(.O (clkfbout_bufg),
.I (clkfbout));

For VHDL

1) Modify the example_design/<core_name>_block.vhd file to add in the MMCM:

a) Add CLOCK_MODULE component

component CLOCK_MODULE is
generic
(
MULT : real := 2.0;
DIVIDE : integer := 2;
CLK_PERIOD : real := 6.4;
OUT0_DIVIDE : real := 2.0;
OUT1_DIVIDE : integer := 2;
OUT2_DIVIDE : integer := 2;
OUT3_DIVIDE : integer := 2
);
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic;
-- Status and control signals
MMCM_RESET_IN : in std_logic;
MMCM_LOCKED_OUT : out std_logic
);
end component;


b) Instantiate the Clock Module:

drpclk_mmcm : CLOCK_MODULE
generic map
(
MULT => 4.0,
DIVIDE => 1,
CLK_PERIOD => 6.4,
OUT0_DIVIDE => 8.0,
OUT1_DIVIDE => 1,
OUT2_DIVIDE => 1,
OUT3_DIVIDE => 1
)
port map
(-- Clock in ports
CLK_IN => clk156_int,
-- Clock out ports
CLK0_OUT => gt0_drpclk_i,
CLK1_OUT => open,
CLK2_OUT => open,
CLK3_OUT => open,
-- Status and control signals
MMCM_RESET_IN => tied_to_ground_i,
MMCM_LOCKED_OUT => open
);

c) Comment out the current GT_USRCLK_SOURCE file and replace it with the following:


gt0_usrclk_source : GT_USRCLK_SOURCE
port map
(
Q1_CLK0_GTREFCLK_PAD_N_IN => Q1_CLK0_GTREFCLK_PAD_N_IN,
Q1_CLK0_GTREFCLK_PAD_P_IN => Q1_CLK0_GTREFCLK_PAD_P_IN,
Q1_CLK0_GTREFCLK_OUT => q1_clk0_refclk_i,

GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
GT0_TXOUTCLK_IN => gt0_txoutclk_i,
GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
DRPCLK_IN => tied_to_ground_i,
DRPCLK_OUT => open
);

2) In example_design/gtx/gt_userclk_source.vhd comment out the BUFR:

-- bufr_inst : BUFR
-- generic map
-- (
-- BUFR_DIVIDE => "2"
-- )
-- port map
-- (
-- I => q1_clk0_gtrefclk,
-- CE => tied_to_vcc_i,
-- CLR => tied_to_ground_i,
-- O => DRPCLK_OUT
-- );

3) In example_design/gtx/clock_module.vhd add a BUFG to the feedback path and connect the input and output ports to the MMCM CLKFBOUT and CLKFBIN ports:

signal clkfbout_bufg : std_logic;

....

CLKFBIN => clkfbout_bufg,

....

clkfb_bufg : BUFG
port map
(O => clkfbout_bufg,
I => clkfbout);

AR# 46053
Date Created 01/30/2012
Last Updated 10/22/2014
Status Active
Type General Article
IP
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