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AR# 46073

13.4 Timing/Speed Files - 7 series FPGAs Trrec_RST has increased


There is a failing timing path associated with the FIFO36E1 Trrec_RST (RST recovery (WRCLK)) when I run timing analysis on my Kintex-7 or Virtex-7 FPGA design. I did not experience this timing failure in previous architectures, nor ISE Design Suite 13.3. Why the change, and is it valid?


The increase in delay is caused by the difference in the reset circuitry for the FIFO36 component in 7 series FPGA verses previous architectures. The FIFO Asynchronous Reset removal time has become smaller than previous architectures, but the recovery time has become much larger. New characterization data based on the latest silicon have also caused this delay to increase between versions of ISE software.

The actual recovery check for the RST pin is when the RST is de-asserted to the CLK active edge, while the WREN pin are also high or asserted within the same WRCLK cycle. The de-assertion of the RST is timed to the next clock edge regardless of WREN pin level. The static timing analysis cannot perform a timing check on the de-assertion of the RST pin with respect to both the CLK active edge and the WREN pin. The static timing analysis does perform a timing check on the worse case situation, which is the de-assertion of the RST pin with respect to the CLK active edge. A timing simulation can be used to see if this recover check will impact the performance or functionality of your design.

If your application does not immediately assert WREN with the de-assertion of the RST and immediately write the first word to the FIFO, your application will not need to analyze this timing check. Or, if your application does not assert the WREN within two WRCLK cycles as the de-assertion of the RST pin, then you do not need to analyze this timing check. To remove this timing check, you can do one of the following:
  • Disable the Timing Check -> UCF: DISABLE = Trrec_RST;
  • False Path the RST Pin -> UCF: PIN my_fifo36.RST TIG;
AR# 46073
Date 02/01/2012
Status Active
Type General Article
  • ISE Design Suite - 13.4