AR# 46089


LogiCORE IP Serial RapidIO Gen2 v1.3 - Incorrect Two Lane Port Support Information in "Port n Control CSR Register" Table


In the LogiCORE IP Serial RapidIO Gen2 v1.3 Product Guide,Table 2-47 describes the Port n Control CSR. In this table, the description for the'Initialized Port Width' field is not correct. The following two items need to be corrected:

  • The "Initialized Port Width" field lists 3'b011 as a reserved value; it should not be reserved. Instead, it should indicate 2x support.
  • Within the "Initialized Port Width" field, a value of 3'b001 is defined as "1x, lane 2"; this isincorrect and should be replaced with "1x, lane R".


The above errors in the product guide are scheduled to be corrected in the next release.Please note that the issue is only in the document; the core itself is correct.

Revision History
02/01/2012 - Initial Release

AR# 46089
Date 05/19/2012
Status Active
Type Known Issues
People Also Viewed