Description

Solution

1. Add an input port to core_name_block and the transceiver called mmcm_locked.
    
2. In the core_name_example_design.v/vhd file:
   1. create the signal mmcm_locked.
   2. connect the signal mmcm_locked to the LOCKED port of MMCM used to generate userclk and userclk2 and to the mmcm_locked input added to the core_name_block.
       
3. In the transceiver.v/vhd file, drive GT0_TXUSERRDY_IN and GT0_RXUSERRDY_IN with mmcm_locked (was previously driven by cplllock).
    
4. In core_name_block.v/vhd, map mmcm_locked to the DCM_LOCKED input port on the core netlist.
    

If using SGMII with the fabric elastic buffer, Comma alignment attributes need to be updated:

(on page 3 of the GUI, select under SGMII Capabilities "10/100/1000 Mb/s" (clock tolerance compliant with Ethernet specification)):
 

If you are using VHDL, change the following  in example_design\transceiver\gtxwizard_gt.vhd:

ALIGN_COMMA_WORD => (1),
CLK_COR_MAX_LAT => (9),
CLK_COR_MIN_LAT => (7),

ALIGN_COMMA_WORD => (2),
CLK_COR_MAX_LAT => (10),
CLK_COR_MIN_LAT => (8),

If you are using Verilog, change the following in example_design\transceiver\gtxwizard_gt.v:

.ALIGN_COMMA_WORD (1),
.CLK_COR_MAX_LAT (9),
.CLK_COR_MIN_LAT (7),

To:

.ALIGN_COMMA_WORD (2),
.CLK_COR_MAX_LAT (10),
.CLK_COR_MIN_LAT (8),