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AR# 46123

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.2 - Changes required to implement on 7-Series General ES silicon


When targeting 7 Series General ES devices, the Ethernet 1000BASE-X PCS/PMA v11.2 core wrapper files need to be updated to not assert the GTX RXUSERRDY or TXUSERRDY until after the MMCM has locked to indicate that the user clocks are valid.

When using SGMII with the Fabric Elastic buffer, the comma alignment needs to be set for a two byte boundary.

Otherwise, the core could fail to correctly clock and cause the fabric elastic buffer to over or under flow.

This solution applies when targeting General ES silicon.

If using Initial ES silicon, the Ethernet 1000BASE-X PCS/PMA v11.1 core should be used and the modification in (Xilinx Answer 44937) should be followed.


To drive the TXUSERRDY and RXUSERRDY with the MMCM locked, make the following updates from the MMCM:
  1. Add an input port to core_name_block and the transceiver called mmcm_locked.
  2. In the core_name_example_design.v/vhd file:
    1. create the signal mmcm_locked.
    2. connect the signal mmcm_locked to the LOCKED port of MMCM used to generate userclk and userclk2 and to the mmcm_locked input added to the core_name_block.
  3. In the transceiver.v/vhd file, drive GT0_TXUSERRDY_IN and GT0_RXUSERRDY_IN with mmcm_locked (was previously driven by cplllock).
  4. In core_name_block.v/vhd, map mmcm_locked to the DCM_LOCKED input port on the core netlist.

If using SGMII with the fabric elastic buffer, Comma alignment attributes need to be updated:

(on page 3 of the GUI, select under SGMII Capabilities "10/100/1000 Mb/s" (clock tolerance compliant with Ethernet specification)):

If you are using VHDL, change the following  in example_design\transceiver\gtxwizard_gt.vhd:



CLK_COR_MAX_LAT => (10),

If you are using Verilog, change the following in example_design\transceiver\gtxwizard_gt.v:




AR# 46123
Date 11/06/2014
Status Active
Type General Article
  • Virtex-7
  • Kintex-7
  • Ethernet 1000BASE-X PCS/PMA or SGMII