AR# 46132


MIG 7 Series DDR3/DDR2 - Trace Matching and Derating Guidelines


The MIG 7 Series DDR3/DDR3 designs require specific trace matching guidelines be followed to ensure the target data rate be achieved. These trace matching guidelines are specified in the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide.

NOTE: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The trace matching requirements specified in the user guide are between:

  • Any DQ and its associated DQS/DQS#
  • Any Address and Control signal and the corresponding CK/CK#
  • CK/CK# and DQS/DQS#

The user guide specifies not only the matching requirements for maximum operation, but how much the guidelines can be loosened for slower interfaces. Refer to the user guide for specific trace matching numbers.

In general, trace lengths should be kept to less than 3 inches.

Additional Information
(Xilinx Answer 51296) Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite Releases
(Xilinx Answer 42024) 7 Series MIG DDR3 - What is the recommended trace impedance between the FPGA and the DDR3 SDRAM?
(Xilinx Answer 58873) MIG 7 Series DDR3 - Automated Trace Matching Checker against MIG 7 Series DDR3 Requirements

Revision History
08/24/12 - Initial release
01/14/14 - Added 58873

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51475 MIG 7 Series Design Assistant - MIG 7 Series DDR2/DDR3, Board Layout and Design Guidelines N/A N/A

Child Answer Records

AR# 46132
Date 01/14/2014
Status Active
Type Solution Center
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