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  1. Xilinx - All Programmable
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  3. AR# 46235: AXI Bridge for PCI Express - x8 gen1 and x4 gen2 do not have a DRC to ensure a 128-bit interface

AR# 46235

AXI Bridge for PCI Express - x8 gen1 and x4 gen2 do not have a DRC to ensure a 128-bit interface

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

The AXI Bridge for PCI Express must use a 128-bit AXI interface when configured as a x8 gen 1 or x4 gen 2.This configuration is only available for 7 series devices.

Solution

The following parameters must be set to 128:

  • C_S_AXI_DATA_WIDTH - In the GUI, this is called: AXI Slave Port Data Width
  • C_M_AXI_DATA_WIDTH - In the GUI, this is called: AXI Master Port Data Width
The EDK tools will allow a bit file to be generated and issue no error.However, this will not work in hardware.A DRC will be added in a future release of the core.

Revision History

03/05/2012 - Corrected link to version resolved AR.
02/08/2012 - Initial Release

NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 46235
Date 05/20/2012
Status Active
Type Known Issues
IP
  • AXI PCI Express (PCIe)