The AXI Bridge for PCI Express must use a 128-bit AXI interface when configured as a x8 gen 1 or x4 gen 2.This configuration is only available for 7 series devices.
The following parameters must be set to 128:
C_S_AXI_DATA_WIDTH - In the GUI, this is called: AXI Slave Port Data Width
C_M_AXI_DATA_WIDTH - In the GUI, this is called: AXI Master Port Data Width
The EDK tools will allow a bit file to be generated and issue no error.However, this will not work in hardware.A DRC will be added in a future release of the core.
03/05/2012 - Corrected link to version resolved AR. 02/08/2012 - Initial Release
NOTE:The "Version Found" columnlists the version that the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.