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AR# 4624

M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of an XC9500 FDCP

Description

Description: The path through the asynchronous preset or clear of

an FDCP in the XC9500 family cannot be analysed using the timing

analyser. The path up to the preset or clear *is* measurable, but not

the path through the flop from the pre/clr to the output.

Solution

The path delay may be calculated manually using the XC9500 timing

model:

tin + tptsr + t aoi + tout

This would be from a pad, through a buffer to the preset/clear, through

the flop, through the output buffer and to the opad.

AR# 4624
Date Created 08/31/2007
Last Updated 01/18/2010
Status Archive
Type General Article