AR# 46327

Partial Reconfiguration - Can a Reconfigurable Partition (RP) region contain static logic?

Description

When a design contains some Partial Reconfiguration modules, is it still possible to place logic from the Static module into the Partial Reconfiguration areas?

Solution

Static logic is permitted to exist in a frame that will be reconfigured, as long as:

It is outside of the area group defined by the Pblock (unless forced inside with a LOC constraint),
And
It does not contain dynamic elements such as block RAM, Distributed (LUT) RAM, or SRLs.

When static logic is placed in a reconfigured frame, the exact functionality of the static logic is rewritten, and is guaranteed not to glitch.

Below is a list of some of the elements that cannot be part of a Partial Reconfiguration module:

Global Clock Buffers, Regional Clock Buffers, and Clock Modifying Blocks must be in static logic.
Device feature blocks must be in static logic, for example: BSCAN, CAPTURE, DCIRESET, FRAME_ECC,ICAP, KEY_CLEAR, STARTUP, USR_ACCESS
All I/Os must reside in static logic.
High speed transceivers must remain in the static Partition.

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Linked Answer Records

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
61201	Vivado Partial Reconfiguration - How do I debug Partial Reconfiguration designs?	N/A	N/A

AR# 46327
Date	01/14/2015
Status	Active
Type	General Article
Devices	FPGA Device Families
Tools	ISE Design Suite PlanAhead Vivado Design Suite

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