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AR# 46345: Virtex-7 485T General ES - Known Issues Master Answer Record
Virtex-7 485T General ES - Known Issues Master Answer Record
This answer record highlights the important requirements and known issues for the Virtex-7 FPGA General Engineering Sample (ES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 485T General ES FPGA devices (XC7V485T GES). Additional silicon limitations might exist, so reference the General ES errata that accompanies the devices.
This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.
ISE 13.4 or higher available on the Xilinx Download Center, is required for use of General ES silicon for Virtex-7 485T devices
Last supported version is ISE 14.3/Vivado 2012.3 Design Suite
Patches - this is the complete list of available patches for ISE/Vivado design suite targeting Virtex-7 General ES silicon
(Xilinx Answer 47816)7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGAs
All 7 Series IP Cores are listed as Pre-production in the CORE Generator "Status" field. Support of Pre-production cores on General ES FPGA devices is dependent on Xilinx hardware validation, which is ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues answer records below for the most recent information. If there are further questions about hardware validation for a particular IP Core, please contact a Field Application Engineer.
All General ES silicon users must update to ISE 13.4 and use the 1000BASE-X PCS/PMA or SGMII v11.2 release
(Xilinx Answer 45677) LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.2 - Release Notes and Known Issues for ISE Design Suite 13.4
MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II
MIG 7 Series users need to use MIG 7 Series v1.4 available with ISE Design Suite 13.4 or later due to updated calibration changes and CKE/ODT implementation changes as outlined in (Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified