This answer record highlights the important requirements and known issues for the Virtex-7 FPGA General Engineering Sample (ES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 485T General ES FPGA devices (XC7V485T GES). Additional silicon limitations might exist, so reference the General ES errata that accompanies the devices.
This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.
Software Requirements
Software Known Issues
IP Requirements
All 7 Series IP Cores are listed as Pre-production in the CORE Generator "Status" field. Support of Pre-production cores on General ES FPGA devices is dependent on Xilinx hardware validation, which is ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues answer records below for the most recent information. If there are further questions about hardware validation for a particular IP Core, please contact a Field Application Engineer.
IP Known Issues
Other Important Items
Revision History
10/05/2012 - Updates for GES
09/24/2012 - Minor update; no change to content
09/18/2012 - Added Other Important Items section
02/23/2012 - Updated IP Known Issues section
02/16/2012 - Initial release
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
51993 | Xilinx 7 Series FPGA Solution Center - Top Issues | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
46370 | Xilinx 7 Series FPGA Solution Center | N/A | N/A |
AR# 46345 | |
---|---|
Date | 10/12/2012 |
Status | Active |
Type | Known Issues |
Devices | |
Tools |