Description

This answer record highlights the important requirements and known issues for the Virtex-7 FPGA General Engineering Sample (ES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 485T General ES FPGA devices (XC7V485T GES). Additional silicon limitations might exist, so reference the General ES errata that accompanies the devices.

This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.

Solution

Software Requirements

• ISE 13.4 or higher available on the Xilinx Download Center, is required for use of General ES silicon for Virtex-7 485T devices
• Last supported version is ISE 14.3/Vivado 2012.3 Design Suite
  
• Patches - this is the complete list of available patches for ISE/Vivado design suite targeting Virtex-7 General ES silicon
  • Required 14.2 patches for all users:
    • (Xilinx Answer 50886) - 14.2/2012.2 Speed Files - Tactical Patch for 7 Series GES -2 Devices
  • Required patches based on usage:
    • (Xilinx Answer 45653) - Required patch if using MIG DDR2/DDR3 memory interface

Software Known Issues

• (Xilinx Answer 40905) - 13.x Software Known Issues Related to the 7 Series FPGA
• (Xilinx Answer 47816)7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGAs

IP Requirements

All 7 Series IP Cores are listed as Pre-production in the CORE Generator "Status" field. Support of Pre-production cores on General ES FPGA devices is dependent on Xilinx hardware validation, which is ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues answer records below for the most recent information. If there are further questions about hardware validation for a particular IP Core, please contact a Field Application Engineer.

IP Known Issues

• 7 Series Integrated Block for PCI Express
  • (Xilinx Answer 40469) 7 Series Integrated Block Wrapper for PCI Express - Release Notes and Known Issues
• XAUI
  • All General ES silicon users must update to ISE 13.4 and use the XAUI v10.2 release
  • (Xilinx Answer 45705) LogiCORE IP XAUI v10.2 - Release Notes and Known Issues for ISE Design Suite 13.4
• Ethernet 1000BASE-X PCS/PMA or SGMII
  • All General ES silicon users must update to ISE 13.4 and use the 1000BASE-X PCS/PMA or SGMII v11.2 release
  • (Xilinx Answer 45677) LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.2 - Release Notes and Known Issues for ISE Design Suite 13.4
• MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II
  • MIG 7 Series users need to use MIG 7 Series v1.4 available with ISE Design Suite 13.4 or later due to updated calibration changes and CKE/ODT implementation changes as outlined in (Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified
  • (Xilinx Answer 45653) Required patch if using MIG DDR2/DDR3 memory interface
  • (Xilinx Answer 45195) MIG 7 Series - Release Notes and Known Issues for all releases

Other Important Items

• (Xilinx Answer 45360) Kintex-7, Virtex-7 GTX Transceiver - Attribute Updates, Issues, and Work-around for General ES Silicon
• (Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices

Revision History

10/05/2012 - Updates for GES
09/24/2012 - Minor update; no change to content
09/18/2012 - Added Other Important Items section
02/23/2012 - Updated IP Known Issues section
02/16/2012 - Initial release

Linked Answer Records

Master Answer Records

Associated Answer Records